From patchwork Mon May 22 15:31:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 684716 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1260578wrt; Mon, 22 May 2023 08:33:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5mQN+JTsEc6G1BWjETxDAAXO5ND33FBskS8X0Fque+3Xq1IMPRjYMj0zx/RKUIn6p2SZLH X-Received: by 2002:a05:622a:3ce:b0:3f6:b218:deb9 with SMTP id k14-20020a05622a03ce00b003f6b218deb9mr3493714qtx.33.1684769608330; Mon, 22 May 2023 08:33:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684769608; cv=none; d=google.com; s=arc-20160816; b=fvLLf2Xs/jn9UCgbZ+Vs7y3y/YS6RY6NSpONKLBkU3bq1c9zcl7FKSrqLQI2g7pW/p LBEyIx8US4Hh8fuYDrXnTYnmKE24Np+D+RqKwXVIdvPCesvCr6rWKNPRn09/Mjcrfu0J VO1OBmxWwa0skkYumtKA+1ojNiKdRBByqYOq8NWfz/gmh0aYzH1yqjCOYGHflkyUvzuQ mTFSxnTy/1vHHV3dA+BA74mHc99BHyy99XALgHeRdXyvLSC69ZRorhWWjgrGvy9bZdrB d3lH1Jy3egbZMbiVpC4LbWAeQeSQnbEiXPS/v4sp9DMtsev5APGcql8gWfq3RT9HE4F2 RCrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PcPyr1Hd/Zw7pAX4B7gZfLX+zfoHJG12lzmzj0tU/xY=; b=xGb0T/zf+YOH0SxjVcMf4daKZLIvq2pA1wTMO3W0UdPqSwsA4DNZSlnH6zJzFSV0kI hO7owmMKDhBOck+Q6DV1JhNbV18SXi4w8usxnaNOcP4gtgkP0GBDLuXwaYXc4ECuOGQM RDc+5hXL9qWA4uox5BLG2tpfNNbsecw9/NghyGwycyKj+UysRQg0+4xYVTBhqkROS6go JfEdUcF2mwyraaDAV5DVuQU1v8j49EVKTrgx9IC+9ZDN670IJ4QZcldqRH0hvC+k6y1f f8UM5SDqbNHMhlePNAFEzRZlDHBvZ9TgGy0DT1V4r6CFQmnOzZrmgAWhLfXr8sDLuwYZ 4Dvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hrPWDhgP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b22-20020a05622a021600b003f53624729bsi3891547qtx.57.2023.05.22.08.33.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 May 2023 08:33:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hrPWDhgP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q17We-0007bz-Bw; Mon, 22 May 2023 11:32:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q17WS-0007Sp-4U for qemu-devel@nongnu.org; Mon, 22 May 2023 11:32:40 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q17WJ-0001QG-Rp for qemu-devel@nongnu.org; Mon, 22 May 2023 11:32:31 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f475366514so42744295e9.2 for ; Mon, 22 May 2023 08:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684769541; x=1687361541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PcPyr1Hd/Zw7pAX4B7gZfLX+zfoHJG12lzmzj0tU/xY=; b=hrPWDhgPUFiBuAMhA5CDRbl9BVs8bETJD7pwCAZ5uhag+rdaBUug4RgowQqjaEhxuM +fSrM+tvfbW9e5Cr3eJIY9N0rjM0VQpSrg6QkPETPvt5EWGG5+jGeeLghnx4DzymM+Nu lR/BBDrel+DVWDmU2r/3TLcPzBDppUkfo/pccf/BWPWf+lxGSaDP2hBKILuouM9OuJLc arCCSLhFVSFQMASuCGNHxBnTBBj4ccKzOM2rCsCFMN3Pmpi5CbZh2ypz5pDkPkUlb5sb YLLcYqiwj28v1nUE8NpWeohdHCcnv8yOGJsNuvGG+y4Dke4tQBnRJYZF2ShR+WQBmIfr yN/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684769541; x=1687361541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PcPyr1Hd/Zw7pAX4B7gZfLX+zfoHJG12lzmzj0tU/xY=; b=PgiEgunFpSVbtpxOiom0IiMx9t1hyg9fTmz17as1jrYkaMWGR0BUWC7BRQRMjf0nj4 ifYziSv0pY7XSyC9oiVguQtPED9sIMKkd2ExUkf9QCPOoD1hrRrxbmiUkoEcEMar46b8 3mz8U8Xq9M0zWCt3XKjFbY9+Y6jAigQIFf83nmdlUTKWmCIO71Sk+2sr1+vrMEWJZSKL ERK9HNg4UOiWxNDoCSC+bBMf8BnAIOLEMA6VeRx7r0mH8eKfCOM+AnKQV8KvM/dFp1tp mlWoQrnDVTSbOLH4chWKMFHyzG8JW3WK2c9F47hc0xk7LUj3TGOEZsf6nN4U4Hx5oSCx BxZw== X-Gm-Message-State: AC+VfDyWhhTSDY5UGgmo5coKeQI/RCOJcb/tQfjM3cbyqaLkoQB685cz uc5EnhGlWXldXHXQQ0WJaO2xb235NxtW+KPFHCo= X-Received: by 2002:a05:600c:220a:b0:3f0:b1c9:25d4 with SMTP id z10-20020a05600c220a00b003f0b1c925d4mr7732831wml.21.1684769541121; Mon, 22 May 2023 08:32:21 -0700 (PDT) Received: from localhost.localdomain ([176.176.153.164]) by smtp.gmail.com with ESMTPSA id f20-20020a7bcd14000000b003f17848673fsm8688467wmj.27.2023.05.22.08.32.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 22 May 2023 08:32:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Alex?= =?utf-8?q?_Benn=C3=A9e?= , Evgeny Iakovlev , =?utf-8?q?Marc-Andr=C3=A9_?= =?utf-8?q?Lureau?= , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 06/12] hw/char/pl011: Replace magic values by register field definitions Date: Mon, 22 May 2023 17:31:38 +0200 Message-Id: <20230522153144.30610-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230522153144.30610-1-philmd@linaro.org> References: <20230522153144.30610-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org 0x400 is Data Register Break Error (DR_BE), 0x10 is Line Control Register Fifo Enabled (LCR_FEN) and 0x1 is Send Break (LCR_BRK). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- hw/char/pl011.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 93e19b2c40..98c5268388 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -54,6 +54,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 +/* Data Register, UARTDR */ +#define DR_BE (1 << 10) + /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ #define INT_OE (1 << 10) #define INT_BE (1 << 9) @@ -69,6 +72,10 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) #define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) +/* Line Control Register, UARTLCR_H */ +#define LCR_FEN (1 << 4) +#define LCR_BRK (1 << 0) + static const unsigned char pl011_id_arm[8] = { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] = @@ -116,7 +123,7 @@ static void pl011_update(PL011State *s) static bool pl011_is_fifo_enabled(PL011State *s) { - return (s->lcr & 0x10) != 0; + return (s->lcr & LCR_FEN) != 0; } static inline unsigned pl011_get_fifo_depth(PL011State *s) @@ -218,7 +225,7 @@ static void pl011_set_read_trigger(PL011State *s) the threshold. However linux only reads the FIFO in response to an interrupt. Triggering the interrupt when the FIFO is non-empty seems to make things work. */ - if (s->lcr & 0x10) + if (s->lcr & LCR_FEN) s->read_trigger = (s->ifl >> 1) & 0x1c; else #endif @@ -281,11 +288,11 @@ static void pl011_write(void *opaque, hwaddr offset, break; case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ - if ((s->lcr ^ value) & 0x10) { + if ((s->lcr ^ value) & LCR_FEN) { pl011_reset_fifo(s); } - if ((s->lcr ^ value) & 0x1) { - int break_enable = value & 0x1; + if ((s->lcr ^ value) & LCR_BRK) { + int break_enable = value & LCR_BRK; qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, &break_enable); } @@ -359,8 +366,9 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size) static void pl011_event(void *opaque, QEMUChrEvent event) { - if (event == CHR_EVENT_BREAK) - pl011_put_fifo(opaque, 0x400); + if (event == CHR_EVENT_BREAK) { + pl011_put_fifo(opaque, DR_BE); + } } static void pl011_clock_update(void *opaque, ClockEvent event)