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[209.51.188.17]) by mx.google.com with ESMTPS id pt1-20020a056214048100b005ab0738009dsi1150418qvb.263.2023.05.18.06.58.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 May 2023 06:58:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=jGoONBGa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pze83-0003t5-1X; Thu, 18 May 2023 09:57:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pze7x-0003ah-3v for qemu-devel@nongnu.org; Thu, 18 May 2023 09:57:09 -0400 Received: from mga12.intel.com ([192.55.52.136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pze7v-0002Nb-DY for qemu-devel@nongnu.org; Thu, 18 May 2023 09:57:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684418227; x=1715954227; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7QNFyBNeGgGdgzd9L+ISvRpqm2xPqBQGWM5cf/izB2Q=; b=jGoONBGaBsgdyqYzRniTG85UiILHgNLXIbXJU/Gs/F5Ax6KpMM2sa3/x 19rn9GgjM62wG1XQM/oy7C+FI0rUfMXmRY+b6ZflSyYvOeH6n5cWqR1JJ Q7oIv1ibVTyQf33b2BKkkHPZmDPulzpyu2V704UANOHMigcjqJ0/kxtQA ERQvhisapIFtFhezdWity/NO2KT259CxTtHSZAdPbRKk+Bn1A9hTRbgHe ArOhTOc7WwFEG1uj3GB+N/cK+sIh6Ql6Plny4WlyyeoljXcXi2raiarCF uDy/kh3T7QV1Fyr1dClv65RXs2JqhKzVsBFlDwV3ooCTWtZVmfUpt/n+f A==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="331685841" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="331685841" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 06:57:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="876428853" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="876428853" Received: from wufei-optiplex-7090.sh.intel.com ([10.238.200.247]) by orsmga005.jf.intel.com with ESMTP; 18 May 2023 06:57:05 -0700 From: Fei Wu To: qemu-devel@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org, fei2.wu@intel.com Cc: Paolo Bonzini Subject: [PATCH v12 11/15] tb-stats: reset the tracked TBs on a tb_flush Date: Thu, 18 May 2023 21:57:53 +0800 Message-Id: <20230518135757.1442654-12-fei2.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518135757.1442654-1-fei2.wu@intel.com> References: <20230518135757.1442654-1-fei2.wu@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=fei2.wu@intel.com; helo=mga12.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Alex Bennée We keep track of translations but can only do so up until the translation cache is flushed. At that point we really have no idea if we can re-create a translation because all the active tracking information has been reset. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Signed-off-by: Fei Wu --- accel/tcg/tb-maint.c | 1 + accel/tcg/tb-stats.c | 19 +++++++++++++++++++ include/exec/tb-stats.h | 8 ++++++++ 3 files changed, 28 insertions(+) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 0980fca358..11ff0ddd90 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -763,6 +763,7 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); tb_remove_all(); + tbstats_reset_tbs(); tcg_region_reset_all(); /* XXX: flush processor icache at this point if cache flush is expensive */ qatomic_inc(&tb_ctx.tb_flush_count); diff --git a/accel/tcg/tb-stats.c b/accel/tcg/tb-stats.c index 55afe6e489..469e3e024b 100644 --- a/accel/tcg/tb-stats.c +++ b/accel/tcg/tb-stats.c @@ -269,6 +269,25 @@ void do_hmp_tbstats_safe(CPUState *cpu, run_on_cpu_data icmd) g_free(cmdinfo); } +/* + * We have to reset the tbs array on a tb_flush as those + * TranslationBlocks no longer exist and we no loner know if the + * current mapping is still valid. + */ + +static void reset_tbs_array(void *p, uint32_t hash, void *userp) +{ + TBStatistics *tbs = p; + g_ptr_array_set_size(tbs->tbs, 0); +} + +void tbstats_reset_tbs(void) +{ + if (tb_ctx.tb_stats.map) { + qht_iter(&tb_ctx.tb_stats, reset_tbs_array, NULL); + } +} + void init_tb_stats_htable(void) { if (!tb_ctx.tb_stats.map && tb_stats_collection_enabled()) { diff --git a/include/exec/tb-stats.h b/include/exec/tb-stats.h index 4bb343870b..30b788f7b2 100644 --- a/include/exec/tb-stats.h +++ b/include/exec/tb-stats.h @@ -124,4 +124,12 @@ struct TbstatsCommand { void do_hmp_tbstats_safe(CPUState *cpu, run_on_cpu_data icmd); +/** + * tbstats_reset_tbs: reset the linked array of TBs + * + * Reset the list of tbs for a given array. Should be called from + * safe work during tb_flush. + */ +void tbstats_reset_tbs(void); + #endif