From patchwork Wed May 17 08:00:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Tokarev X-Patchwork-Id: 682909 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp231171wrt; Wed, 17 May 2023 01:11:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7NmiQyutLdxpIrfaKsWssKCKf/eF6M8KQfjOE9G7nzsDhr7mLHTG9BojGT588iGlVUWfgN X-Received: by 2002:a05:622a:211:b0:3ef:3511:f494 with SMTP id b17-20020a05622a021100b003ef3511f494mr69471734qtx.16.1684311076796; Wed, 17 May 2023 01:11:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684311076; cv=none; d=google.com; s=arc-20160816; b=0jBOMGhQRDNbiQ3T25qpG3TqCcPvdHMdauPyGesnxQ3DllZzY3Ix9Erk7nfGQk0xHp MTQAip0xERnK0h7IY7X3f5iQMC9g9IDHGYDx8tHeIuAE+6epYXPt4lze2v908daIA8rD 2oPd59wST3kzBHqAcfSxkDrpOXRLMT1nNkWoK8yv4p5nHu3Qol5KMhPB9/DSEr2HOfyC EY0/j/5t7Zuu5xqdJfUHI2XDJtHM5H/ook/cTrKsP2VZEQwqtIZV3t5BoCH9Now1cBXW jb8OOrKLRl6LQn7J3kNuGldoI95kp5X5lVZJPhCP5h8AXfmglOnryzvBWQEwX5XZ4hVw dKWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=GamS3+Kc+NwOXwImuX97lvHh6uivd76pqWR7sL14SgE=; b=q3RyuA26jacLVe9afluFBxThzbyGkVRR2z7E8Nwjt/0TWoR1ieJLDju2i8zaFI+npd rXCaU5Bq8Z1+x7Vh1nwnFhfqmX9npVJcIsTGdyvmmmtNqXUPUi5Yb5i+2k9JK3baM1G0 wiJGJAd/z+/qe5Ed4BkNFGgljgkMn8K6orAe5P+/DB3rq2ckAPLrWxHTnhuZ2O6F25rw et9gkeO9yu2VKb9BTyIs3gNa1FzhwE+I3bB4HAMW7TahjOkUiIr7ST+qB8n4+Wfe7XI4 g0XI1N3c60zFM9nAhdBGfUyO5EjibnKMsv37FFozqL3fpe34gK4Sqw2ufjhZ2jPYgz+C mMlg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t17-20020ac85891000000b003f3908aec16si12361680qta.687.2023.05.17.01.11.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 May 2023 01:11:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzC6c-0002Yq-RB; Wed, 17 May 2023 04:01:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6J-00022j-W5; Wed, 17 May 2023 04:01:36 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzC6F-0000Zj-IY; Wed, 17 May 2023 04:01:35 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id D70166757; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 5D47E5E0F; Wed, 17 May 2023 11:00:58 +0300 (MSK) Received: (nullmailer pid 3624120 invoked by uid 1000); Wed, 17 May 2023 08:00:56 -0000 From: Michael Tokarev To: qemu-stable@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v8.0.1 14/36] hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit() Date: Wed, 17 May 2023 11:00:34 +0300 Message-Id: <20230517080056.3623993-14-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <<20230517073442.3622973-0-mjt@msgid.tls.msk.ru> References: <20230517073442.3622973-0-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Peter Maydell The Allwinner PIC model uses set_bit() and clear_bit() to update the values in its irq_pending[] array when an interrupt arrives. However it is using these functions wrongly: they work on an array of type 'long', and it is passing an array of type 'uint32_t'. Because the code manually figures out the right array element, this works on little-endian hosts and on 32-bit big-endian hosts, where bits 0..31 in a 'long' are in the same place as they are in a 'uint32_t'. However it breaks on 64-bit big-endian hosts. Remove the use of set_bit() and clear_bit() in favour of using deposit32() on the array element. This fixes a bug where on big-endian 64-bit hosts the guest kernel would hang early on in bootup. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-id: 20230424152833.1334136-1-peter.maydell@linaro.org (cherry picked from commit 2c5fa0778c3b4307f9f3af7f27886c46d129c62f) Signed-off-by: Michael Tokarev --- hw/intc/allwinner-a10-pic.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 8cca124807..4875e68ba6 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -49,12 +49,9 @@ static void aw_a10_pic_update(AwA10PICState *s) static void aw_a10_pic_set_irq(void *opaque, int irq, int level) { AwA10PICState *s = opaque; + uint32_t *pending_reg = &s->irq_pending[irq / 32]; - if (level) { - set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); - } else { - clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); - } + *pending_reg = deposit32(*pending_reg, irq % 32, 1, level); aw_a10_pic_update(s); }