diff mbox series

[PULL,43/53] target/mips: Use MO_ALIGN instead of 0

Message ID	20230511080450.860923-44-richard.henderson@linaro.org
State	Accepted
Commit	fc49723769dca4edf1348e1eec96ad4b810260ba
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 43/53] target/mips: Use MO_ALIGN instead of 0 Date: Thu, 11 May 2023 09:04:40 +0100 Message-Id: <20230511080450.860923-44-richard.henderson@linaro.org> In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/53] target/m68k: Fix gen_load_fp for OS_LONG \| expand [PULL,01/53] target/m68k: Fix gen_load_fp for OS_LONG [PULL,02/53] accel/tcg: Fix atomic_mmu_lookup for reads [PULL,03/53] disas: Fix tabs and braces in disas.c [PULL,04/53] disas: Move disas.c to disas/ [PULL,05/53] disas: Remove target_ulong from the interface [PULL,06/53] disas: Remove target-specific headers [PULL,07/53] disas: Move softmmu specific code to separate file [PULL,08/53] disas: Move disas.c into the target-independent source set [PULL,09/53] cpu: expose qemu_cpu_list_lock for lock-guard use [PULL,10/53] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount [PULL,11/53] tcg/i386: Introduce prepare_host_addr [PULL,12/53] tcg/i386: Use indexed addressing for softmmu fast path [PULL,13/53] tcg/aarch64: Introduce prepare_host_addr [PULL,14/53] tcg/arm: Introduce prepare_host_addr [PULL,15/53] tcg/loongarch64: Introduce prepare_host_addr [PULL,16/53] tcg/mips: Introduce prepare_host_addr [PULL,17/53] tcg/ppc: Introduce prepare_host_addr [PULL,18/53] tcg/riscv: Introduce prepare_host_addr [PULL,19/53] tcg/s390x: Introduce prepare_host_addr [PULL,20/53] tcg: Add routines for calling slow-path helpers [PULL,21/53] tcg/i386: Convert tcg_out_qemu_ld_slow_path [PULL,22/53] tcg/i386: Convert tcg_out_qemu_st_slow_path [PULL,23/53] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path [PULL,24/53] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path [PULL,25/53] tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path [PULL,26/53] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path [PULL,27/53] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path [PULL,28/53] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path [PULL,29/53] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path [PULL,30/53] tcg/loongarch64: Simplify constraints on qemu_ld/st [PULL,31/53] tcg/mips: Remove MO_BSWAP handling [PULL,32/53] tcg/mips: Reorg tlb load within prepare_host_addr [PULL,33/53] tcg/mips: Simplify constraints on qemu_ld/st [PULL,34/53] tcg/ppc: Reorg tcg_out_tlb_read [PULL,35/53] tcg/ppc: Adjust constraints on qemu_ld/st [PULL,36/53] tcg/ppc: Remove unused constraints A, B, C, D [PULL,37/53] tcg/ppc: Remove unused constraint J [PULL,38/53] tcg/riscv: Simplify constraints on qemu_ld/st [PULL,39/53] tcg/s390x: Use ALGFR in constructing softmmu host address [PULL,40/53] tcg/s390x: Simplify constraints on qemu_ld/st [PULL,41/53] target/mips: Add MO_ALIGN to gen_llwp, gen_scwp [PULL,42/53] target/mips: Add missing default_tcg_memop_mask [PULL,43/53] target/mips: Use MO_ALIGN instead of 0 [PULL,44/53] target/mips: Remove TARGET_ALIGNED_ONLY [PULL,45/53] target/nios2: Remove TARGET_ALIGNED_ONLY [PULL,46/53] target/sh4: Use MO_ALIGN where required [PULL,47/53] target/sh4: Remove TARGET_ALIGNED_ONLY [PULL,48/53] tcg: Remove TARGET_ALIGNED_ONLY [PULL,49/53] accel/tcg: Add cpu_in_serial_context [PULL,50/53] accel/tcg: Introduce tlb_read_idx [PULL,51/53] accel/tcg: Reorg system mode load helpers [PULL,52/53] accel/tcg: Reorg system mode store helpers [PULL,53/53] target/loongarch: Do not include tcg-ldst.h

Commit Message

Richard Henderson May 11, 2023, 8:04 a.m. UTC

The opposite of MO_UNALN is MO_ALIGN.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/tcg/nanomips_translate.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index b96dcd2ae9..a98dde0d2e 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -4305,7 +4305,7 @@  static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     TCGv va = tcg_temp_new();
                     TCGv t1 = tcg_temp_new();
                     MemOp memop = (extract32(ctx->opcode, 8, 3)) ==
-                                      NM_P_LS_UAWM ? MO_UNALN : 0;
+                                      NM_P_LS_UAWM ? MO_UNALN : MO_ALIGN;
 
                     count = (count == 0) ? 8 : count;
                     while (counter != count) {