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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:46 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Date: Fri, 5 May 2023 11:02:13 +1000 Message-Id: <20230505010241.21812-62-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Merge with mstatus_{fs,vs}. We might perform a redundant assignment to one or the other field, but it's a trivial and saves 4 bits from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 16 +++++++--------- target/riscv/cpu_helper.c | 33 ++++++++++++++++----------------- target/riscv/translate.c | 32 ++++++++++---------------------- 3 files changed, 33 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51d39687fe..ab64d5f92d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -644,19 +644,17 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 15, 1) -FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) -FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 20, 2) +FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) -FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) -FIELD(TB_FLAGS, VTA, 24, 1) -FIELD(TB_FLAGS, VMA, 25, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) +FIELD(TB_FLAGS, VTA, 20, 1) +FIELD(TB_FLAGS, VMA, 21, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 26, 1) +FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1) +FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8412ef26ee..e3e620137b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -45,7 +45,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, { CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); - + RISCVExtStatus fs, vs; uint32_t flags = 0; *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; @@ -79,18 +79,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, } #ifdef CONFIG_USER_ONLY - flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY); - flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY); + fs = EXT_STATUS_DIRTY; + vs = EXT_STATUS_DIRTY; #else flags |= cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags = FIELD_DP32(flags, TB_FLAGS, FS, - get_field(env->mstatus, MSTATUS_FS)); - } - if (riscv_cpu_vector_enabled(env)) { - flags = FIELD_DP32(flags, TB_FLAGS, VS, - get_field(env->mstatus, MSTATUS_VS)); - } + fs = get_field(env->mstatus, MSTATUS_FS); + vs = get_field(env->mstatus, MSTATUS_VS); if (riscv_has_ext(env, RVH)) { if (env->priv == PRV_M || @@ -100,18 +94,23 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - - flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, - get_field(env->mstatus_hs, MSTATUS_VS)); - flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enabled); + if (env->virt_enabled) { + flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } } if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif + flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) { flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 411e771e6f..3092c942ab 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -66,8 +66,6 @@ typedef struct DisasContext { uint32_t opcode; RISCVExtStatus mstatus_fs; RISCVExtStatus mstatus_vs; - RISCVExtStatus mstatus_hs_fs; - RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -620,16 +618,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } - - if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs = EXT_STATUS_DIRTY; - tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } } } #else @@ -653,16 +647,12 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } - - if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs = EXT_STATUS_DIRTY; - tmp = tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } } } #else @@ -1171,8 +1161,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->cfg_ptr = &(cpu->cfg); - ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); - ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);