| Message ID | 20230503070656.1746170-52-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Improve atomicity support | expand |
On Wed, 3 May 2023 at 08:13, Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/sparc64/tcg-target.c.inc | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc > index bb23038529..4f9ec02b1f 100644 > --- a/tcg/sparc64/tcg-target.c.inc > +++ b/tcg/sparc64/tcg-target.c.inc > @@ -1028,11 +1028,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, > { > TCGLabelQemuLdst *ldst = NULL; > MemOp opc = get_memop(oi); > - unsigned a_bits = get_alignment_bits(opc); > - unsigned s_bits = opc & MO_SIZE; > + MemOp s_bits = opc & MO_SIZE; > + MemOp a_bits, atom_a, atom_u; > unsigned a_mask; > > /* We don't support unaligned accesses. */ > + a_bits = atom_and_align_for_opc(s, &atom_a, &atom_u, opc, > + MO_ATOM_IFALIGN, false); > a_bits = MAX(a_bits, s_bits); > a_mask = (1u << a_bits) - 1; > > -- No changes to HostAddress struct again? -- PMM
On 5/5/23 14:20, Peter Maydell wrote: > On Wed, 3 May 2023 at 08:13, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> tcg/sparc64/tcg-target.c.inc | 6 ++++-- >> 1 file changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc >> index bb23038529..4f9ec02b1f 100644 >> --- a/tcg/sparc64/tcg-target.c.inc >> +++ b/tcg/sparc64/tcg-target.c.inc >> @@ -1028,11 +1028,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, >> { >> TCGLabelQemuLdst *ldst = NULL; >> MemOp opc = get_memop(oi); >> - unsigned a_bits = get_alignment_bits(opc); >> - unsigned s_bits = opc & MO_SIZE; >> + MemOp s_bits = opc & MO_SIZE; >> + MemOp a_bits, atom_a, atom_u; >> unsigned a_mask; >> >> /* We don't support unaligned accesses. */ >> + a_bits = atom_and_align_for_opc(s, &atom_a, &atom_u, opc, >> + MO_ATOM_IFALIGN, false); >> a_bits = MAX(a_bits, s_bits); >> a_mask = (1u << a_bits) - 1; >> >> -- > > No changes to HostAddress struct again? Again, no use of alignment outside of prepare_host_addr. No 128-bit operations, and all host operations aligned. r~
diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index bb23038529..4f9ec02b1f 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1028,11 +1028,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, { TCGLabelQemuLdst *ldst = NULL; MemOp opc = get_memop(oi); - unsigned a_bits = get_alignment_bits(opc); - unsigned s_bits = opc & MO_SIZE; + MemOp s_bits = opc & MO_SIZE; + MemOp a_bits, atom_a, atom_u; unsigned a_mask; /* We don't support unaligned accesses. */ + a_bits = atom_and_align_for_opc(s, &atom_a, &atom_u, opc, + MO_ATOM_IFALIGN, false); a_bits = MAX(a_bits, s_bits); a_mask = (1u << a_bits) - 1;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/sparc64/tcg-target.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)