@@ -932,24 +932,26 @@ typedef struct TCGArgConstraint {
/* Bits for TCGOpDef->flags, 8 bits available, all used. */
enum {
+ /* Two bits describing the output type. */
+ TCG_OPF_TYPE_MASK = 0x03,
+ TCG_OPF_32BIT = 0x00,
+ TCG_OPF_64BIT = 0x01,
+ TCG_OPF_VECTOR = 0x02,
+ TCG_OPF_128BIT = 0x03,
/* Instruction exits the translation block. */
- TCG_OPF_BB_EXIT = 0x01,
+ TCG_OPF_BB_EXIT = 0x04,
/* Instruction defines the end of a basic block. */
- TCG_OPF_BB_END = 0x02,
+ TCG_OPF_BB_END = 0x08,
/* Instruction clobbers call registers and potentially update globals. */
- TCG_OPF_CALL_CLOBBER = 0x04,
+ TCG_OPF_CALL_CLOBBER = 0x10,
/* Instruction has side effects: it cannot be removed if its outputs
are not used, and might trigger exceptions. */
- TCG_OPF_SIDE_EFFECTS = 0x08,
- /* Instruction operands are 64-bits (otherwise 32-bits). */
- TCG_OPF_64BIT = 0x10,
+ TCG_OPF_SIDE_EFFECTS = 0x20,
/* Instruction is optional and not implemented by the host, or insn
is generic and should not be implemened by the host. */
- TCG_OPF_NOT_PRESENT = 0x20,
- /* Instruction operands are vectors. */
- TCG_OPF_VECTOR = 0x40,
+ TCG_OPF_NOT_PRESENT = 0x40,
/* Instruction is a conditional branch. */
- TCG_OPF_COND_BRANCH = 0x80
+ TCG_OPF_COND_BRANCH = 0x80,
};
typedef struct TCGOpDef {
@@ -2051,12 +2051,21 @@ void tcg_optimize(TCGContext *s)
copy_propagate(&ctx, op, def->nb_oargs, def->nb_iargs);
/* Pre-compute the type of the operation. */
- if (def->flags & TCG_OPF_VECTOR) {
+ switch (def->flags & TCG_OPF_TYPE_MASK) {
+ case TCG_OPF_VECTOR:
ctx.type = TCG_TYPE_V64 + TCGOP_VECL(op);
- } else if (def->flags & TCG_OPF_64BIT) {
+ break;
+ case TCG_OPF_128BIT:
+ ctx.type = TCG_TYPE_I128;
+ break;
+ case TCG_OPF_64BIT:
ctx.type = TCG_TYPE_I64;
- } else {
+ break;
+ case TCG_OPF_32BIT:
ctx.type = TCG_TYPE_I32;
+ break;
+ default:
+ qemu_build_not_reached();
}
/* Assume all bits affected, no bits known zero, no sign reps. */
@@ -2294,7 +2294,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
nb_iargs = def->nb_iargs;
nb_cargs = def->nb_cargs;
- if (def->flags & TCG_OPF_VECTOR) {
+ if ((def->flags & TCG_OPF_TYPE_MASK) == TCG_OPF_VECTOR) {
col += ne_fprintf(f, "v%d,e%d,", 64 << TCGOP_VECL(op),
8 << TCGOP_VECE(op));
}
@@ -4782,7 +4782,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
tcg_out_extrl_i64_i32(s, new_args[0], new_args[1]);
break;
default:
- if (def->flags & TCG_OPF_VECTOR) {
+ if ((def->flags & TCG_OPF_TYPE_MASK) == TCG_OPF_VECTOR) {
tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
new_args, const_args);
} else {
@@ -1921,9 +1921,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
- /* 99% of the time, we can signal the use of extension registers
- by looking to see if the opcode handles 64-bit data. */
- TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
+ /*
+ * 99% of the time, we can signal the use of extension registers
+ * by looking to see if the opcode handles 32-bit data or not.
+ */
+ TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_TYPE_MASK) != TCG_OPF_32BIT;
/* Hoist the loads of the most common arguments. */
TCGArg a0 = args[0];
@@ -790,7 +790,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
{
TCGArg pos = args[2], len = args[3];
- TCGArg max = tcg_op_defs[opc].flags & TCG_OPF_64BIT ? 64 : 32;
+ TCGArg max = ((tcg_op_defs[opc].flags & TCG_OPF_TYPE_MASK)
+ == TCG_OPF_32BIT ? 32 : 64);
tcg_debug_assert(pos < max);
tcg_debug_assert(pos + len <= max);