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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id g10-20020a7bc4ca000000b003f171234a08sm35040330wmk.20.2023.05.02.05.15.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 May 2023 05:15:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/35] target/arm: Add compile time asserts to load/store_cpu_field macros Date: Tue, 2 May 2023 13:14:57 +0100 Message-Id: <20230502121459.2422303-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230502121459.2422303-1-peter.maydell@linaro.org> References: <20230502121459.2422303-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add some compile-time asserts to the load_cpu_field() and store_cpu_field() macros that the struct field being accessed is the expected size. This lets us catch cases where we incorrectly tried to do a 32-bit load from a 64-bit struct field. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230424153909.1419369-3-peter.maydell@linaro.org --- target/arm/translate-a32.h | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 99eea85fa86..48a15379d22 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -59,7 +59,12 @@ static inline TCGv_i32 load_cpu_offset(int offset) return tmp; } -#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) +/* Load from a 32-bit field to a TCGv_i32 */ +#define load_cpu_field(name) \ + ({ \ + QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4); \ + load_cpu_offset(offsetof(CPUARMState, name)); \ + }) /* Load from the low half of a 64-bit field to a TCGv_i32 */ #define load_cpu_field_low32(name) \ @@ -70,9 +75,13 @@ static inline TCGv_i32 load_cpu_offset(int offset) void store_cpu_offset(TCGv_i32 var, int offset, int size); -#define store_cpu_field(var, name) \ - store_cpu_offset(var, offsetof(CPUARMState, name), \ - sizeof_field(CPUARMState, name)) +#define store_cpu_field(val, name) \ + ({ \ + QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, name) != 4 \ + && sizeof_field(CPUARMState, name) != 1); \ + store_cpu_offset(val, offsetof(CPUARMState, name), \ + sizeof_field(CPUARMState, name)); \ + }) #define store_cpu_field_constant(val, name) \ store_cpu_field(tcg_constant_i32(val), name)