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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c22c800b003ef71d541cbsm4673752wmg.1.2023.04.14.09.04.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 09:04:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 3/3] target/arm: handle ipa_secure vs s2walk_secure correctly Date: Fri, 14 Apr 2023 17:04:13 +0100 Message-Id: <20230414160413.549801-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414160413.549801-1-peter.maydell@linaro.org> References: <20230414160413.549801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In get_phys_addr_twostage() when we set up the stage 2 translation, we currently incorrectly set all of in_mmu_idx, in_ptw_idx and in_secure based on s2walk_secure. Here s2walk_secure is true if we should be doing this stage 2 walk to physical memory. ipa_secure is true if the intermediate physical address we got from stage 1 is secure. The VSTCR_EL2.SW and VTCR_EL2.NSW bits allow the guest to configure secure EL2 so that these two things are different, eg: * a stage 2 walk for an NS IPA done to secure physical memory (where the translation table base address and other parameters for the walk come from the NS control registers VTTBR_EL2 and VTCR_EL2) * a stage 2 walk for an S IPA done to non-secure physical memory (where the parameters from the walk come from the S control registers VSTTBR_EL2 and VSTCR_EL2) To tell get_phys_addr_lpae() to do this, we need to pass in an in_mmu_idx based on ipa_secure, and an in_ptw_idx based on s2walk_secure. The in_secure parameter follows in_mmu_idx, as usual. Note that this change relies on fixes in the previous two commits ("Don't allow stage 2 page table walks to downgrade to NS" and "Set ptw->out_secure correctly for stage 2 translations"). Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- This change also means that v8M, which also uses get_phys_addr_twostage(), is no longer using a ptw->in_mmu_idx calculated based on s2walk_secure, which was always a little strange given that v8M doesn't do any kind of s2 walk, even though it didn't produce incorrect behaviour. --- target/arm/ptw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c1e124df495..2ee2b0b9241 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2741,9 +2741,9 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, } is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; - ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; - ptw->in_secure = s2walk_secure; + ptw->in_secure = ipa_secure; /* * S1 is done, now do S2 translation.