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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv Date: Wed, 12 Apr 2023 13:43:21 +0200 Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org> --- target/riscv/internals.h | 9 +++++++++ target/riscv/cpu_helper.c | 6 +----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 0b61f337dd..4aa1cb409f 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,15 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) +static inline int mmuidx_priv(int mmu_idx) +{ + int ret = mmu_idx & 3; + if (ret == MMUIdx_S_SUM) { + ret = PRV_S; + } + return ret; +} + static inline bool mmuidx_sum(int mmu_idx) { return (mmu_idx & 3) == MMUIdx_S_SUM; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 29ee9b1b42..57bb19c76e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, */ MemTxResult res; MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; - int mode = env->priv; + int mode = mmuidx_priv(mmu_idx); bool use_background = false; hwaddr ppn; int napot_bits = 0; @@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode = get_field(env->hstatus, HSTATUS_SPVP); - } else if (mode == PRV_M && access_type != MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode = get_field(env->mstatus, MSTATUS_MPP); - } } if (first_stage == false) {