[v7,13/25] target/riscv: Introduce mmuidx_priv

Message ID	20230412114333.118895-14-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com> Subject: [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv Date: Wed, 12 Apr 2023 13:43:21 +0200 Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org> In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/riscv: MSTATUS_SUM + cleanups \| expand [v7,00/25] target/riscv: MSTATUS_SUM + cleanups [v7,01/25] target/riscv: Extract virt enabled state from tb flags [v7,02/25] target/riscv: Add a general status enum for extensions [v7,03/25] target/riscv: Encode the FS and VS on a normal way for tb flags [v7,04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags [v7,05/25] target/riscv: Add a tb flags field for vstart [v7,06/25] target/riscv: Separate priv from mmu_idx [v7,07/25] target/riscv: Reduce overhead of MSTATUS_SUM change [v7,08/25] accel/tcg: Add cpu_ld_code_mmu [v7,09/25] target/riscv: Use cpu_ld_code_mmu for HLVX [v7,10/25] target/riscv: Handle HLV, HSV via helpers [v7,11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT [v7,12/25] target/riscv: Introduce mmuidx_sum [v7,13/25] target/riscv: Introduce mmuidx_priv [v7,14/25] target/riscv: Introduce mmuidx_2stage [v7,15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv [v7,16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index [v7,17/25] target/riscv: Check SUM in the correct register [v7,18/25] target/riscv: Hoist second stage mode change to callers [v7,19/25] target/riscv: Hoist pbmte and hade out of the level loop [v7,20/25] target/riscv: Move leaf pte processing out of level loop [v7,21/25] target/riscv: Suppress pte update with is_debug [v7,22/25] target/riscv: Don't modify SUM with is_debug [v7,23/25] target/riscv: Merge checks for reserved pte flags [v7,24/25] target/riscv: Reorg access check in get_physical_address [v7,25/25] target/riscv: Reorg sum check in get_physical_address

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20230412114333.118895-14-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
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 Alistair Francis <alistair.francis@wdc.com>,
 Weiwei Li <liweiwei@iscas.ac.cn>,
 Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv
Date: Wed, 12 Apr 2023 13:43:21 +0200
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Series

target/riscv: MSTATUS_SUM + cleanups | expand

Commit Message

Richard Henderson April 12, 2023, 11:43 a.m. UTC

Use the priv level encoded into the mmu_idx, rather than
starting from env->priv.  We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org>
---
 target/riscv/internals.h  | 9 +++++++++
 target/riscv/cpu_helper.c | 6 +-----
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 0b61f337dd..4aa1cb409f 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -37,6 +37,15 @@ 
 #define MMUIdx_M            3
 #define MMU_2STAGE_BIT      (1 << 2)
 
+static inline int mmuidx_priv(int mmu_idx)
+{
+    int ret = mmu_idx & 3;
+    if (ret == MMUIdx_S_SUM) {
+        ret = PRV_S;
+    }
+    return ret;
+}
+
 static inline bool mmuidx_sum(int mmu_idx)
 {
     return (mmu_idx & 3) == MMUIdx_S_SUM;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 29ee9b1b42..57bb19c76e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -758,7 +758,7 @@  static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      */
     MemTxResult res;
     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
-    int mode = env->priv;
+    int mode = mmuidx_priv(mmu_idx);
     bool use_background = false;
     hwaddr ppn;
     int napot_bits = 0;
@@ -781,10 +781,6 @@  static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      */
     if (riscv_cpu_two_stage_lookup(mmu_idx)) {
         mode = get_field(env->hstatus, HSTATUS_SPVP);
-    } else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-        if (get_field(env->mstatus, MSTATUS_MPRV)) {
-            mode = get_field(env->mstatus, MSTATUS_MPP);
-        }
     }
 
     if (first_stage == false) {

[v7,13/25] target/riscv: Introduce mmuidx_priv

Commit Message

Patch