From patchwork Wed Apr 12 11:43:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 672617 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:184:0:0:0:0 with SMTP id p4csp288187wrx; Wed, 12 Apr 2023 04:46:45 -0700 (PDT) X-Google-Smtp-Source: AKy350bGGw6UF4hSkdCCwC8gexBFo1x9iJdrAjFmmtawp0OR1u/efrO49JUPPrYPHKRefinLtvCW X-Received: by 2002:a05:622a:ca:b0:3bf:d8b6:4ca1 with SMTP id p10-20020a05622a00ca00b003bfd8b64ca1mr29474846qtw.28.1681300005197; Wed, 12 Apr 2023 04:46:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681300005; cv=none; d=google.com; s=arc-20160816; b=pCeYBW6JhEzPne43DY0ichoxBSYVE4ePn85jmLSRlJpDsrO0VL5W+1FWvcPTlY3voK VKrNqa7bOuuKuNqja9HyxG9SvCK0PMpxW80zVQfxwm876o1P6aw9niSnXFRsavVjCnSd lDDwqXxINgcXImxGaFjZR2mHi3hlTEQx4oG9+YTgayXCQHsk39utkwAVKkfny4cR39CY M1t9+Lj2P/x7iBF8EkRU76t76zlL5V99B70dk8E5rtQLc7koJoOcvLIktNTXjCUc8ic4 pbBLGcSdKOIOk3IT7jRjMSZqIWGd8Sn5685jJPwqHk3yP39VSc7WxONX2IR/EKL7ib1i Psfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=d5xHxmaEOgXeHn2A8bHUUouqfxAhC2pmFZSPjP/T4RA=; b=Id2BaZ3zeSqOxLSzbZs0Adnt8whVeB5phyG3V8V6ao2GmvIq0WizdmOqb7gZUBbOXX If93accXDyXfr4a8ndoLUtLrYecXWkYEkvOxfigOzj+NsbHld4vCvVjeW0fxQ0ujR3Xb hPKvm+QYbuM2QEuL+GEEH59d0KshZ2YrinbV8n1MFlk8iexySv1I9ABTIlPewhTYDIvg 8Tf1pz+ML+1DNhlyf+09ZqrNc9y5kFmgmI4mM6bMTl4c74Gkonl2xJHjCMHUG7F/8Hx9 85AeP1hABGP+m9Vu+YqoPOsatNb5vXCEwh0NsDN/K1Zmw5IY/09zl7UfS9qgsBKUrKc5 Ps2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iUFz6FMN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e22-20020a05622a111600b003bd00fdf974si10818829qty.9.2023.04.12.04.46.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Apr 2023 04:46:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iUFz6FMN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYte-0005nN-4E; Wed, 12 Apr 2023 07:44:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtB-0004rG-2j for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:49 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYt9-0002QF-6w for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:48 -0400 Received: by mail-wr1-x436.google.com with SMTP id j11so14219544wrd.2 for ; Wed, 12 Apr 2023 04:43:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299825; x=1683891825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d5xHxmaEOgXeHn2A8bHUUouqfxAhC2pmFZSPjP/T4RA=; b=iUFz6FMNJKOwmKWjet0a5BDbOC5RP1/hvbzKia/CJNC51T0WUDnyNUtoW2yCKYdG8O m9+SPinDpvdG9KU4qwEsJXozVJJF3CB2pLxyf52CXZfL6P6v0TELHRmsAb6YdGi8LIxY EMi2CzNH8ZtBzDKlvukANZENiWe1qZ3OosWsTwKBlU3R+I7gkPs/kgP394NMeCHNluCQ JTuW+gLChrF134ow9A0WVK33F0rlXQYMyDXJ7VuBLjaF1d8y2YHUmGK8M+3w5OzikwW8 5bms+kTZrBUl2Q5joojdDXJs1Q0C0k+KF9UavbY1sC/MhaoYAD6PGOsOqrNibK8kymKF 0M5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299825; x=1683891825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d5xHxmaEOgXeHn2A8bHUUouqfxAhC2pmFZSPjP/T4RA=; b=I7D04VYVkLZruxBPAWDi2/nuHlX8XaUKQA8Yzds7wDTLd3MzuFV+13zNVSJSyc8j4Y +FsEOvre+u54apjpK5c8dO1SyT0Jj4Q8ODRt7Y4Va5ypZKxkrXTMuZBIUwJr9tCiPtTH GU/o1P8X5TEb6IrdTn6EaqVrWlveXqSm2uXrqQfJimOg4cGbGON2SFoIe/uAlmAKKTqD MKDy+cN3C7hFpLUqpNwpPGSHPS/mO2JZ4CMxF0Sv4ozB5tI1a2b7IoieCbSxso3U4GO5 /FnFg7W3ii95fopEaSrn0PU0S36Np1w6x8h/wISWtqokLNt/bYOFjE9YchRsPUw7dLe7 G7/Q== X-Gm-Message-State: AAQBX9e7p0lGYAOA4Bq4t354Bspuv8EWRVk2txw2Yp9/d0R9m1vUw+ml sI2ClekNR5oCY+KKcjMPdcwhXhCcJOAtaut0qOy7VdNV X-Received: by 2002:adf:e34c:0:b0:2e5:a86c:fe74 with SMTP id n12-20020adfe34c000000b002e5a86cfe74mr8403377wrj.51.1681299824828; Wed, 12 Apr 2023 04:43:44 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Date: Wed, 12 Apr 2023 13:43:19 +0200 Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org> --- target/riscv/internals.h | 6 ++++-- target/riscv/cpu_helper.c | 2 +- target/riscv/op_helper.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b55152a7dc..7b63c0f1b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -27,13 +27,15 @@ * - S 0b001 * - S+SUM 0b010 * - M 0b011 - * - HLV/HLVX/HSV adds 0b100 + * - U+2STAGE 0b100 + * - S+2STAGE 0b101 + * - S+SUM+2STAGE 0b110 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 -#define MMU_HYP_ACCESS_BIT (1 << 2) +#define MMU_2STAGE_BIT (1 << 2) /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index abf275d2c6..291a1acbf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -593,7 +593,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & MMU_HYP_ACCESS_BIT; + return mmu_idx & MMU_2STAGE_BIT; } int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 663382785e..a5de3daee7 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; + return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)