[v2,04/54] tcg: Split out tcg_out_ext8u

Message ID	20230411010512.5375-5-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 04/54] tcg: Split out tcg_out_ext8u Date: Mon, 10 Apr 2023 18:04:22 -0700 Message-Id: <20230411010512.5375-5-richard.henderson@linaro.org> In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org> References: <20230411010512.5375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Simplify calls to load/store helpers \| expand [v2,00/54] tcg: Simplify calls to load/store helpers [v2,01/54] tcg: Replace if + tcg_abort with tcg_debug_assert [v2,02/54] tcg: Replace tcg_abort with g_assert_not_reached [v2,03/54] tcg: Split out tcg_out_ext8s [v2,04/54] tcg: Split out tcg_out_ext8u [v2,05/54] tcg: Split out tcg_out_ext16s [v2,06/54] tcg: Split out tcg_out_ext16u [v2,07/54] tcg: Split out tcg_out_ext32s [v2,08/54] tcg: Split out tcg_out_ext32u [v2,09/54] tcg: Split out tcg_out_exts_i32_i64 [v2,10/54] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 [v2,11/54] tcg/mips: Conditionalize tcg_out_exts_i32_i64 [v2,12/54] tcg/riscv: Conditionalize tcg_out_exts_i32_i64 [v2,13/54] tcg: Split out tcg_out_extu_i32_i64 [v2,14/54] tcg/i386: Conditionalize tcg_out_extu_i32_i64 [v2,15/54] tcg: Split out tcg_out_extrl_i64_i32 [v2,16/54] tcg: Introduce tcg_out_movext [v2,17/54] tcg: Introduce tcg_out_xchg [v2,18/54] tcg: Introduce tcg_out_movext2 [v2,19/54] tcg: Clear TCGLabelQemuLdst on allocation [v2,20/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} [v2,21/54] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} [v2,22/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} [v2,23/54] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} [v2,24/54] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} [v2,25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} [v2,26/54] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} [v2,27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 [v2,28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} [v2,29/54] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return [v2,30/54] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} [v2,31/54] tcg: Move TCGLabelQemuLdst to tcg.c [v2,32/54] tcg: Replace REG_P with arg_loc_reg_p [v2,33/54] tcg: Introduce arg_slot_stk_ofs [v2,34/54] tcg: Widen helper_*_st[bw]_mmu val arguments [v2,35/54] tcg: Add routines for calling slow-path helpers [v2,36/54] tcg/i386: Convert tcg_out_qemu_ld_slow_path [v2,37/54] tcg/i386: Convert tcg_out_qemu_st_slow_path [v2,38/54] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path [v2,39/54] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path [v2,40/54] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path [v2,41/54] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path [v2,42/54] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path [v2,43/54] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path [v2,44/54] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path [v2,45/54] tcg/loongarch64: Simplify constraints on qemu_ld/st [v2,46/54] tcg/mips: Remove MO_BSWAP handling [v2,47/54] tcg/mips: Reorg tcg_out_tlb_load [v2,48/54] tcg/mips: Simplify constraints on qemu_ld/st [v2,49/54] tcg/ppc: Reorg tcg_out_tlb_read [v2,50/54] tcg/ppc: Adjust constraints on qemu_ld/st [v2,51/54] tcg/ppc: Remove unused constraints A, B, C, D [v2,52/54] tcg/riscv: Simplify constraints on qemu_ld/st [v2,53/54] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st [v2,54/54] tcg/s390x: Simplify constraints on qemu_ld/st

diff --git a/tcg/tcg.c b/tcg/tcg.c index 76ba3e28cd..b02ffc5679 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -106,6 +106,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); +static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4504,6 +4505,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) case INDEX_op_ext8s_i64: tcg_out_ext8s(s, TCG_TYPE_I64, new_args[0], new_args[1]); break; + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + tcg_out_ext8u(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4f4f814293..cca91363ce 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1432,6 +1432,11 @@ static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, tcg_out_ubfm(s, 0, rd, rn, 0, bits); } +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_uxt(s, MO_8, rd, rn); +} + static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, int64_t aimm) { @@ -2243,10 +2248,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); break; - case INDEX_op_ext8u_i64: - case INDEX_op_ext8u_i32: - tcg_out_uxt(s, MO_8, a0, a1); - break; case INDEX_op_ext16u_i64: case INDEX_op_ext16u_i32: tcg_out_uxt(s, MO_16, a0, a1); @@ -2313,6 +2314,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 04a860897f..b99f08a54b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -964,8 +964,13 @@ static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); } +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); +} + static void __attribute__((unused)) -tcg_out_ext8u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) +tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } @@ -1365,8 +1370,8 @@ static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \ DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u, - (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) +DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond, + (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u, (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg = TCG_REG_TMP)) DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) @@ -2299,6 +2304,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8u_i32: default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 14e8bdf56b..462a2348c6 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1259,7 +1259,7 @@ static inline void tcg_out_rolw_8(TCGContext *s, int reg) tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); } -static inline void tcg_out_ext8u(TCGContext *s, int dest, int src) +static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) { /* movzbl */ tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS == 64); @@ -2673,9 +2673,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, OP_32_64(ext16s): tcg_out_ext16s(s, a0, a1, rexw); break; - OP_32_64(ext8u): - tcg_out_ext8u(s, a0, a1); - break; OP_32_64(ext16u): tcg_out_ext16u(s, a0, a1); break; @@ -2840,6 +2837,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index a96f655c44..a206b9cfc5 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1246,11 +1246,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - tcg_out_ext8u(s, a0, a1); - break; - case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: tcg_out_ext16s(s, a0, a1); @@ -1624,6 +1619,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 8fc9d02bd5..5a712e3da5 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -558,6 +558,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); } +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1099,7 +1104,7 @@ static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { tmp = tcg_target_call_iarg_regs[i]; } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); + tcg_out_ext8u(s, tmp, arg); return tcg_out_call_iarg_reg(s, i, tmp); } @@ -2423,6 +2428,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 573067e535..ec8e5a1a8a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -780,6 +780,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) tcg_out32(s, EXTSB | RA(dst) | RS(src)); } +static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) +{ + tcg_out32(s, ANDI | SAI(src, dst, 0xff)); +} + static inline void tcg_out_ext16s(TCGContext *s, TCGReg dst, TCGReg src) { tcg_out32(s, EXTSH | RA(dst) | RS(src)); @@ -3123,6 +3128,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 04b27f6887..d9b08014ce 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1597,11 +1597,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - tcg_out_ext8u(s, a0, a1); - break; - case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: tcg_out_ext16u(s, a0, a1); @@ -1648,6 +1643,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 1232ccb122..338a91c591 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1097,7 +1097,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) tcg_out_insn(s, RRE, LGBR, dest, src); } -static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) +static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) { tcg_out_insn(s, RRE, LLGCR, dest, src); } @@ -1153,7 +1153,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) return; } if ((val & valid) == 0xff) { - tgen_ext8u(s, TCG_TYPE_I64, dest, dest); + tcg_out_ext8u(s, dest, dest); return; } if ((val & valid) == 0xffff) { @@ -1806,7 +1806,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) } switch (opc & MO_SIZE) { case MO_UB: - tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); + tcg_out_ext8u(s, TCG_REG_R4, data_reg); break; case MO_UW: tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); @@ -2236,9 +2236,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i32: tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); break; - case INDEX_op_ext8u_i32: - tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); - break; case INDEX_op_ext16u_i32: tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); break; @@ -2541,9 +2538,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: tgen_ext32s(s, args[0], args[1]); break; - case INDEX_op_ext8u_i64: - tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); - break; case INDEX_op_ext16u_i64: tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); break; @@ -2640,6 +2634,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 7952cfc4da..4792b04b54 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -501,6 +501,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) g_assert_not_reached(); } +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -883,7 +888,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op) */ switch (op & MO_SIZE) { case MO_8: - tcg_out_arithi(s, r, r, 0xff, ARITH_AND); + tcg_out_ext8u(s, r, r); break; case MO_16: tcg_out_arithi(s, r, r, 16, SHIFT_SLL); @@ -1707,6 +1712,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 029508e308..e946d9165e 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -575,6 +575,17 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) } } +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + if (TCG_TARGET_REG_BITS == 64) { + tcg_debug_assert(TCG_TARGET_HAS_ext8u_i64); + tcg_out_op_rr(s, INDEX_op_ext8u_i64, rd, rs); + } else { + tcg_debug_assert(TCG_TARGET_HAS_ext8u_i32); + tcg_out_op_rr(s, INDEX_op_ext8u_i32, rd, rs); + } +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -733,7 +744,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ @@ -814,6 +824,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); }

[v2,04/54] tcg: Split out tcg_out_ext8u

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