Message ID | 20230411010512.5375-13-richard.henderson@linaro.org |
---|---|
State | Superseded |
Headers | show
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[40.133.238.146]) by smtp.gmail.com with ESMTPSA id s10-20020a65690a000000b0051b0e564963sm1320291pgq.49.2023.04.10.18.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 18:05:46 -0700 (PDT) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 12/54] tcg/riscv: Conditionalize tcg_out_exts_i32_i64 Date: Mon, 10 Apr 2023 18:04:30 -0700 Message-Id: <20230411010512.5375-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org> References: <20230411010512.5375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
tcg: Simplify calls to load/store helpers
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expand
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On 4/10/23 22:04, Richard Henderson wrote: > Since TCG_TYPE_I32 values are kept sign-extended in registers, > via "w" instructions, we need not extend if the register matches. Perhaps "we don't need to extend if ..." ? > This is already relied upon by comparisons. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > tcg/riscv/tcg-target.c.inc | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 7bd3b421ad..2b9aab29ec 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -604,7 +604,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) > > static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) > { > - tcg_out_ext32s(s, ret, arg); > + if (ret != arg) { > + tcg_out_ext32s(s, ret, arg); > + } > } > > static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 7bd3b421ad..2b9aab29ec 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -604,7 +604,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_out_ext32s(s, ret, arg); + if (ret != arg) { + tcg_out_ext32s(s, ret, arg); + } } static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
Since TCG_TYPE_I32 values are kept sign-extended in registers, via "w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)