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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id o11-20020a05600c4fcb00b003ebff290a52sm2565572wmq.28.2023.04.05.09.05.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 09:05:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , David Gibson , Greg Kurz Subject: [PATCH 08/10] target/ppc: Restrict KVM-specific field from ArchCPU Date: Wed, 5 Apr 2023 18:04:52 +0200 Message-Id: <20230405160454.97436-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405160454.97436-1-philmd@linaro.org> References: <20230405160454.97436-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The 'kvm_sw_tlb' field shouldn't be accessed when KVM is not available. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 2 ++ target/ppc/mmu_common.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 557d736dab..0ec3957397 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1148,7 +1148,9 @@ struct CPUArchState { int tlb_type; /* Type of TLB we're dealing with */ ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ bool tlb_dirty; /* Set to non-zero when modifying TLB */ +#ifdef CONFIG_KVM bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ +#endif /* CONFIG_KVM */ uint32_t tlb_need_flush; /* Delayed flush needed */ #define TLB_NEED_LOCAL_FLUSH 0x1 #define TLB_NEED_GLOBAL_FLUSH 0x2 diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 7235a4befe..21843c69f6 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -917,10 +917,12 @@ static void mmubooke_dump_mmu(CPUPPCState *env) ppcemb_tlb_t *entry; int i; +#ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { qemu_printf("Cannot access KVM TLB\n"); return; } +#endif qemu_printf("\nTLB:\n"); qemu_printf("Effective Physical Size PID Prot " @@ -1008,10 +1010,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env) int offset = 0; int i; +#ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { qemu_printf("Cannot access KVM TLB\n"); return; } +#endif for (i = 0; i < BOOKE206_MAX_TLBN; i++) { int size = booke206_tlb_size(env, i);