| Message ID | 20230325105429.1142530-12-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: MSTATUS_SUM + cleanups | expand |
On Sat, Mar 25, 2023 at 9:57 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > We will enable more uses of this bit in the future. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/internals.h | 6 ++++-- > target/riscv/cpu_helper.c | 2 +- > target/riscv/op_helper.c | 2 +- > 3 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/internals.h b/target/riscv/internals.h > index b55152a7dc..7b63c0f1b6 100644 > --- a/target/riscv/internals.h > +++ b/target/riscv/internals.h > @@ -27,13 +27,15 @@ > * - S 0b001 > * - S+SUM 0b010 > * - M 0b011 > - * - HLV/HLVX/HSV adds 0b100 > + * - U+2STAGE 0b100 > + * - S+2STAGE 0b101 > + * - S+SUM+2STAGE 0b110 > */ > #define MMUIdx_U 0 > #define MMUIdx_S 1 > #define MMUIdx_S_SUM 2 > #define MMUIdx_M 3 > -#define MMU_HYP_ACCESS_BIT (1 << 2) > +#define MMU_2STAGE_BIT (1 << 2) > > /* share data between vector helpers and decode code */ > FIELD(VDATA, VM, 0, 1) > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9bb84be4e1..888f7ae0ef 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -605,7 +605,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) > > bool riscv_cpu_two_stage_lookup(int mmu_idx) > { > - return mmu_idx & MMU_HYP_ACCESS_BIT; > + return mmu_idx & MMU_2STAGE_BIT; > } > > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 0f81645adf..81362537b6 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); > } > > - return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; > + return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; > } > > target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) > -- > 2.34.1 > >
diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b55152a7dc..7b63c0f1b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -27,13 +27,15 @@ * - S 0b001 * - S+SUM 0b010 * - M 0b011 - * - HLV/HLVX/HSV adds 0b100 + * - U+2STAGE 0b100 + * - S+2STAGE 0b101 + * - S+SUM+2STAGE 0b110 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 -#define MMU_HYP_ACCESS_BIT (1 << 2) +#define MMU_2STAGE_BIT (1 << 2) /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9bb84be4e1..888f7ae0ef 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -605,7 +605,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & MMU_HYP_ACCESS_BIT; + return mmu_idx & MMU_2STAGE_BIT; } int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 0f81645adf..81362537b6 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; + return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)
We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/internals.h | 6 ++++-- target/riscv/cpu_helper.c | 2 +- target/riscv/op_helper.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-)