diff mbox series

[PULL,v2,59/91] target/sh4: Avoid tcg_const_i32 for TAS.B

Message ID	20230309200550.3878088-60-richard.henderson@linaro.org
State	Accepted
Commit	d3c2b2b3664e33f058adcd662410262ed18402a1
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL v2 59/91] target/sh4: Avoid tcg_const_i32 for TAS.B Date: Thu, 9 Mar 2023 12:05:18 -0800 Message-Id: <20230309200550.3878088-60-richard.henderson@linaro.org> In-Reply-To: <20230309200550.3878088-1-richard.henderson@linaro.org> References: <20230309200550.3878088-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,v2,01/91] target/mips: Drop tcg_temp_free from micromips_translate.c.inc \| expand [PULL,v2,01/91] target/mips: Drop tcg_temp_free from micromips_translate.c.inc [PULL,v2,02/91] target/mips: Drop tcg_temp_free from msa_translate.c [PULL,v2,03/91] target/mips: Drop tcg_temp_free from mxu_translate.c [PULL,v2,04/91] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc [PULL,v2,05/91] target/mips: Drop tcg_temp_free from octeon_translate.c [PULL,v2,06/91] target/mips: Drop tcg_temp_free from translate_addr_const.c [PULL,v2,07/91] target/mips: Drop tcg_temp_free from tx79_translate.c [PULL,v2,08/91] target/mips: Drop tcg_temp_free from vr54xx_translate.c [PULL,v2,09/91] target/mips: Drop tcg_temp_free from translate.c [PULL,v2,10/91] target/s390x: Drop free_compare [PULL,v2,11/91] target/s390x: Drop tcg_temp_free from translate_vx.c.inc [PULL,v2,12/91] target/s390x: Drop tcg_temp_free from translate.c [PULL,v2,13/91] target/s390x: Remove assert vs g_in2 [PULL,v2,14/91] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext [PULL,v2,15/91] tcg: Create tcg/tcg-temp-internal.h [PULL,v2,16/91] include/exec: Set default `NB_MMU_MODES` to 16 [PULL,v2,17/91] target/alpha: Remove `NB_MMU_MODES` define [PULL,v2,18/91] target/arm: Remove `NB_MMU_MODES` define [PULL,v2,19/91] target/avr: Remove `NB_MMU_MODES` define [PULL,v2,20/91] target/cris: Remove `NB_MMU_MODES` define [PULL,v2,21/91] target/hexagon: Remove `NB_MMU_MODES` define [PULL,v2,22/91] target/hppa: Remove `NB_MMU_MODES` define [PULL,v2,23/91] target/i386: Remove `NB_MMU_MODES` define [PULL,v2,24/91] target/loongarch: Remove `NB_MMU_MODES` define [PULL,v2,25/91] target/m68k: Remove `NB_MMU_MODES` define [PULL,v2,26/91] target/microblaze: Remove `NB_MMU_MODES` define [PULL,v2,27/91] target/mips: Remove `NB_MMU_MODES` define [PULL,v2,28/91] target/nios2: Remove `NB_MMU_MODES` define [PULL,v2,29/91] target/openrisc: Remove `NB_MMU_MODES` define [PULL,v2,30/91] target/ppc: Remove `NB_MMU_MODES` define [PULL,v2,31/91] target/riscv: Remove `NB_MMU_MODES` define [PULL,v2,32/91] target/rx: Remove `NB_MMU_MODES` define [PULL,v2,33/91] target/s390x: Remove `NB_MMU_MODES` define [PULL,v2,34/91] target/sh4: Remove `NB_MMU_MODES` define [PULL,v2,35/91] target/sparc: Remove `NB_MMU_MODES` define [PULL,v2,36/91] target/tricore: Remove `NB_MMU_MODES` define [PULL,v2,37/91] target/xtensa: Remove `NB_MMU_MODES` define [PULL,v2,38/91] include/exec: Remove guards around `NB_MMU_MODES` [PULL,v2,39/91] target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS [PULL,v2,40/91] target/avr: Avoid use of tcg_const_i32 throughout [PULL,v2,41/91] target/cris: Avoid use of tcg_const_i32 throughout [PULL,v2,42/91] target/hppa: Avoid tcg_const_i64 in trans_fid_f [PULL,v2,43/91] target/hppa: Avoid use of tcg_const_i32 throughout [PULL,v2,44/91] target/i386: Avoid use of tcg_const_* throughout [PULL,v2,45/91] target/m68k: Avoid tcg_const_i32 when modified [PULL,v2,46/91] target/m68k: Avoid tcg_const_i32 in bfop_reg [PULL,v2,47/91] target/m68k: Avoid tcg_const_* throughout [PULL,v2,48/91] target/mips: Split out gen_lxl [PULL,v2,49/91] target/mips: Split out gen_lxr [PULL,v2,50/91] target/mips: Avoid tcg_const_tl in gen_r6_ld [PULL,v2,51/91] target/mips: Avoid tcg_const_* throughout [PULL,v2,52/91] target/ppc: Split out gen_vx_vmul10 [PULL,v2,53/91] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad [PULL,v2,54/91] target/rx: Use tcg_gen_abs_i32 [PULL,v2,55/91] target/rx: Use cpu_psw_z as temp in flags computation [PULL,v2,56/91] target/rx: Avoid tcg_const_i32 when new temp needed [PULL,v2,57/91] target/rx: Avoid tcg_const_i32 [PULL,v2,58/91] target/s390x: Avoid tcg_const_i64 [PULL,v2,59/91] target/sh4: Avoid tcg_const_i32 for TAS.B [PULL,v2,60/91] target/sh4: Avoid tcg_const_i32 [PULL,v2,61/91] tcg/sparc: Avoid tcg_const_tl in gen_edge [PULL,v2,62/91] target/tricore: Split t_n as constant from temp as variable [PULL,v2,63/91] target/tricore: Rename t_off10 and use tcg_constant_i32 [PULL,v2,64/91] target/tricore: Use setcondi instead of explicit allocation [PULL,v2,65/91] target/tricore: Drop some temp initialization [PULL,v2,66/91] target/tricore: Avoid tcg_const_i32 [PULL,v2,67/91] tcg: Replace tcg_const_i64 in tcg-op.c [PULL,v2,68/91] target/arm: Use rmode >= 0 for need_rmode [PULL,v2,69/91] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf [PULL,v2,70/91] target/arm: Improve arm_rmode_to_sf [PULL,v2,71/91] target/arm: Consistently use ARMFPRounding during translation [PULL,v2,72/91] target/arm: Create gen_set_rmode, gen_restore_rmode [PULL,v2,73/91] target/arm: Improve trans_BFCI [PULL,v2,74/91] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} [PULL,v2,75/91] target/arm: Avoid tcg_const_* in translate-mve.c [PULL,v2,76/91] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn [PULL,v2,77/91] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn [PULL,v2,78/91] target/arm: Avoid tcg_const_ptr in handle_rev [PULL,v2,79/91] target/m68k: Use tcg_constant_i32 in gen_ea_mode [PULL,v2,80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb [PULL,v2,81/91] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc [PULL,v2,82/91] target/ppc: Avoid tcg_const_* in xxeval [PULL,v2,83/91] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc [PULL,v2,84/91] target/ppc: Avoid tcg_const_* in fp-impl.c.inc [PULL,v2,85/91] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc [PULL,v2,86/91] target/ppc: Rewrite trans_ADDG6S [PULL,v2,87/91] target/ppc: Fix gen_tlbsx_booke206 [PULL,v2,88/91] target/ppc: Avoid tcg_const_* in translate.c [PULL,v2,89/91] target/tricore: Use min/max for saturate [PULL,v2,90/91] tcg: Drop tcg_const__vec [PULL,v2,91/91] tcg: Drop tcg_const_

Commit Message

Richard Henderson March 9, 2023, 8:05 p.m. UTC

Since we're assigning to cpu_sr_t in the end,
use that as the intermediate temp as well.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/translate.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff mbox series

Patch

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ad6de41712..70a45c26e8 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1610,12 +1610,9 @@  static void _decode_opc(DisasContext * ctx)
 	tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
 	return;
     case 0x401b:		/* tas.b @Rn */
-        {
-            TCGv val = tcg_const_i32(0x80);
-            tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val,
-                                        ctx->memidx, MO_UB);
-            tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
-        }
+        tcg_gen_atomic_fetch_or_i32(cpu_sr_t, REG(B11_8),
+                                    tcg_constant_i32(0x80), ctx->memidx, MO_UB);
+        tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0);
         return;
     case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
 	CHECK_FPU_ENABLED