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([2602:ae:154a:9f01:87cc:49bb:2900:c08b]) by smtp.gmail.com with ESMTPSA id r13-20020a17090b050d00b002372106a5c2sm6567901pjz.37.2023.03.05.16.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Mar 2023 16:40:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 07/84] softmmu: Check watchpoints for read+write at once Date: Sun, 5 Mar 2023 16:38:37 -0800 Message-Id: <20230306003954.1866998-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230306003954.1866998-1-richard.henderson@linaro.org> References: <20230306003954.1866998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Atomic operations are read-modify-write, and we'd like to be able to test both read and write with one call. This is easy enough, with BP_MEM_READ | BP_MEM_WRITE. Add BP_HIT_SHIFT to make it easy to set BP_WATCHPOINT_HIT_*. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 7 ++++--- softmmu/watchpoint.c | 19 ++++++++++--------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fb5d9667ca..75689bff02 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -923,9 +923,10 @@ void cpu_single_step(CPUState *cpu, int enabled); #define BP_GDB 0x10 #define BP_CPU 0x20 #define BP_ANY (BP_GDB | BP_CPU) -#define BP_WATCHPOINT_HIT_READ 0x40 -#define BP_WATCHPOINT_HIT_WRITE 0x80 -#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) +#define BP_HIT_SHIFT 6 +#define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) +#define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) +#define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint); diff --git a/softmmu/watchpoint.c b/softmmu/watchpoint.c index 279129dd1c..ad58736787 100644 --- a/softmmu/watchpoint.c +++ b/softmmu/watchpoint.c @@ -162,9 +162,12 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, /* this is currently used only by ARM BE32 */ addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); } + + assert((flags & ~BP_MEM_ACCESS) == 0); QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (watchpoint_address_matches(wp, addr, len) - && (wp->flags & flags)) { + int hit_flags = wp->flags & flags; + + if (hit_flags && watchpoint_address_matches(wp, addr, len)) { if (replay_running_debug()) { /* * replay_breakpoint reads icount. @@ -184,16 +187,14 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, replay_breakpoint(); return; } - if (flags == BP_MEM_READ) { - wp->flags |= BP_WATCHPOINT_HIT_READ; - } else { - wp->flags |= BP_WATCHPOINT_HIT_WRITE; - } + + wp->flags |= hit_flags << BP_HIT_SHIFT; wp->hitaddr = MAX(addr, wp->vaddr); wp->hitattrs = attrs; - if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint && - !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { + if (wp->flags & BP_CPU + && cc->tcg_ops->debug_check_watchpoint + && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { wp->flags &= ~BP_WATCHPOINT_HIT; continue; }