[PULL,42/84] target/loongarch: Drop tcg_temp_free

Message ID	20230306003954.1866998-43-richard.henderson@linaro.org
State	Accepted
Commit	34aac056a4fa144f0b297e9b796c2d8e22e83aae
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Song Gao <gaosong@loongson.cn> Subject: [PULL 42/84] target/loongarch: Drop tcg_temp_free Date: Sun, 5 Mar 2023 16:39:12 -0800 Message-Id: <20230306003954.1866998-43-richard.henderson@linaro.org> In-Reply-To: <20230306003954.1866998-1-richard.henderson@linaro.org> References: <20230306003954.1866998-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/84] tcg: Include "qemu/timer.h" for profile_getclock \| expand [PULL,01/84] tcg: Include "qemu/timer.h" for profile_getclock [PULL,02/84] tcg: Link branches to the labels [PULL,03/84] tcg: Merge two sequential labels [PULL,04/84] target/sparc: Use tlb_set_page_full [PULL,05/84] accel/tcg: Retain prot flags from tlb_fill [PULL,06/84] accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookup [PULL,07/84] softmmu: Check watchpoints for read+write at once [PULL,08/84] accel/tcg: Trigger watchpoints from atomic_mmu_lookup [PULL,09/84] include/qemu/cpuid: Introduce xgetbv_low [PULL,10/84] tcg/i386: Mark Win64 call-saved vector regs as reserved [PULL,11/84] tcg: Decode the operand to INDEX_op_mb in dumps [PULL,12/84] tcg: Remove tcg_check_temp_count, tcg_clear_temp_count [PULL,13/84] accel/tcg: Remove translator_loop_temp_check [PULL,14/84] target/alpha: Drop tcg_temp_free [PULL,15/84] target/arm: Remove arm_free_cc, a64_free_cc [PULL,16/84] target/arm: Remove value_global from DisasCompare [PULL,17/84] target/arm: Drop tcg_temp_free from translator.c [PULL,18/84] target/arm: Drop DisasContext.tmp_a64 [PULL,19/84] target/arm: Drop new_tmp_a64 [PULL,20/84] target/arm: Drop new_tmp_a64_zero [PULL,21/84] target/arm: Drop tcg_temp_free from translator-a64.c [PULL,22/84] target/arm: Drop tcg_temp_free from translator-m-nocp.c [PULL,23/84] target/arm: Drop tcg_temp_free from translator-mve.c [PULL,24/84] target/arm: Drop tcg_temp_free from translator-neon.c [PULL,25/84] target/arm: Drop tcg_temp_free from translator-sme.c [PULL,26/84] target/arm: Drop tcg_temp_free from translator-sve.c [PULL,27/84] target/arm: Drop tcg_temp_free from translator-vfp.c [PULL,28/84] target/arm: Drop tcg_temp_free from translator.h [PULL,29/84] target/avr: Drop DisasContext.free_skip_var0 [PULL,30/84] target/avr: Drop R from trans_COM [PULL,31/84] target/avr: Drop tcg_temp_free [PULL,32/84] target/cris: Drop cris_alu_free_temps [PULL,33/84] target/cris: Drop cris_alu_m_free_temps [PULL,34/84] target/cris: Drop addr from dec10_ind_move_m_pr [PULL,35/84] target/cris: Drop tcg_temp_free [PULL,36/84] target/hexagon: Drop tcg_temp_free from C code [PULL,37/84] target/hexagon: Drop tcg_temp_free from gen_tcg_funcs.py [PULL,38/84] target/hexagon/idef-parser: Drop tcg_temp_free [PULL,39/84] target/hexagon/idef-parser: Drop HexValue.is_manual [PULL,40/84] target/hppa: Drop tcg_temp_free [PULL,41/84] target/loongarch: Drop temp_new [PULL,42/84] target/loongarch: Drop tcg_temp_free [PULL,43/84] target/m68k: Drop mark_to_release [PULL,44/84] target/m68k: Drop free_cond [PULL,45/84] target/m68k: Drop tcg_temp_free [PULL,46/84] target/microblaze: Drop tcg_temp_free [PULL,47/84] target/nios2: Drop tcg_temp_free [PULL,48/84] target/openrisc: Drop tcg_temp_free [PULL,49/84] target/ppc: Drop tcg_temp_free [PULL,50/84] target/riscv: Drop ftemp_new [PULL,51/84] target/riscv: Drop temp_new [PULL,52/84] target/riscv: Drop tcg_temp_free [PULL,53/84] target/rx: Drop tcg_temp_free [PULL,54/84] target/sh4: Drop tcg_temp_free [PULL,55/84] target/sparc: Drop get_temp_tl [PULL,56/84] target/sparc: Drop get_temp_i32 [PULL,57/84] target/sparc: Remove egress label in disas_sparc_context [PULL,58/84] target/sparc: Drop free_compare [PULL,59/84] target/sparc: Drop tcg_temp_free [PULL,60/84] target/xtensa: Drop reset_sar_tracker [PULL,61/84] target/xtensa: Drop tcg_temp_free [PULL,62/84] target/i386: Drop tcg_temp_free [PULL,63/84] target/mips: Drop tcg_temp_free from mips16e_translate.c.inc [PULL,64/84] target/mips: Fix trans_mult_acc return [PULL,65/84] target/tricore: Drop tcg_temp_free [PULL,66/84] include/exec/gen-icount: Drop tcg_temp_free in gen_tb_start [PULL,67/84] tracing: remove transform.py [PULL,68/84] docs/devel/tcg-ops: Drop recommendation to free temps [PULL,69/84] target/hexagon: Use tcg_constant_* for gen_constant_from_imm [PULL,70/84] target/hexagon/idef-parser: Use gen_tmp for LPCFG [PULL,71/84] target/hexagon/idef-parser: Use gen_tmp for gen_pred_assign [PULL,72/84] target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_pred [PULL,73/84] target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_op [PULL,74/84] target/i386: Simplify POPF [PULL,75/84] target/microblaze: Avoid tcg_const_* throughout [PULL,76/84] target/riscv: Avoid tcg_const_* [PULL,77/84] target/s390x: Split out gen_ri2 [PULL,78/84] target/sparc: Avoid tcg_const_{tl,i32} [PULL,79/84] target/xtensa: Tidy translate_bb [PULL,80/84] target/xtensa: Tidy translate_clamps [PULL,81/84] target/xtensa: Avoid tcg_const_i32 in translate_l32r [PULL,82/84] target/xtensa: Use tcg_gen_subfi_i32 in translate_sll [PULL,83/84] target/xtensa: Split constant in bit shift [PULL,84/84] target/xtensa: Avoid tcg_const_i32

diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc index 8e45eadbc8..43d6cf261d 100644 --- a/target/loongarch/insn_trans/trans_arith.c.inc +++ b/target/loongarch/insn_trans/trans_arith.c.inc @@ -100,14 +100,12 @@ static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src2) { TCGv discard = tcg_temp_new(); tcg_gen_muls2_tl(discard, dest, src1, src2); - tcg_temp_free(discard); } static void gen_mulh_du(TCGv dest, TCGv src1, TCGv src2) { TCGv discard = tcg_temp_new(); tcg_gen_mulu2_tl(discard, dest, src1, src2); - tcg_temp_free(discard); } static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2) @@ -129,9 +127,6 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2) tcg_gen_and_tl(ret, ret, t0); tcg_gen_or_tl(ret, ret, t1); tcg_gen_movcond_tl(TCG_COND_NE, ret, ret, zero, ret, src2); - - tcg_temp_free(t0); - tcg_temp_free(t1); } static void prep_divisor_du(TCGv ret, TCGv src2) @@ -152,7 +147,6 @@ static void gen_div_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); prep_divisor_d(t0, src1, src2); tcg_gen_div_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2) @@ -160,7 +154,6 @@ static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); prep_divisor_d(t0, src1, src2); tcg_gen_rem_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_div_du(TCGv dest, TCGv src1, TCGv src2) @@ -168,7 +161,6 @@ static void gen_div_du(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); prep_divisor_du(t0, src2); tcg_gen_divu_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2) @@ -176,7 +168,6 @@ static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); prep_divisor_du(t0, src2); tcg_gen_remu_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_div_w(TCGv dest, TCGv src1, TCGv src2) @@ -185,7 +176,6 @@ static void gen_div_w(TCGv dest, TCGv src1, TCGv src2) /* We need not check for integer overflow for div_w. */ prep_divisor_du(t0, src2); tcg_gen_div_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2) @@ -194,7 +184,6 @@ static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2) /* We need not check for integer overflow for rem_w. */ prep_divisor_du(t0, src2); tcg_gen_rem_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa) @@ -202,7 +191,6 @@ static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa) TCGv t0 = tcg_temp_new(); tcg_gen_shli_tl(t0, src1, sa); tcg_gen_add_tl(dest, t0, src2); - tcg_temp_free(t0); } static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a) diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc index 6763c1c301..612709f2a7 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -14,7 +14,6 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); gen_set_gpr(a->rd, dest, EXT_NONE); - tcg_temp_free(t0); return true; } @@ -43,8 +42,6 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop) tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval); gen_set_label(done); gen_set_gpr(a->rd, dest, EXT_NONE); - tcg_temp_free(t0); - tcg_temp_free(val); return true; } diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc index b01e4aeb23..25b4d7858b 100644 --- a/target/loongarch/insn_trans/trans_bit.c.inc +++ b/target/loongarch/insn_trans/trans_bit.c.inc @@ -122,9 +122,6 @@ static void gen_revb_2h(TCGv dest, TCGv src1) tcg_gen_and_tl(t1, src1, mask); tcg_gen_shli_tl(t1, t1, 8); tcg_gen_or_tl(dest, t0, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_revb_4h(TCGv dest, TCGv src1) @@ -138,9 +135,6 @@ static void gen_revb_4h(TCGv dest, TCGv src1) tcg_gen_and_tl(t1, src1, mask); tcg_gen_shli_tl(t1, t1, 8); tcg_gen_or_tl(dest, t0, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_revh_2w(TCGv dest, TCGv src1) @@ -154,9 +148,6 @@ static void gen_revh_2w(TCGv dest, TCGv src1) tcg_gen_and_i64(t0, t0, mask); tcg_gen_shli_i64(t1, t1, 16); tcg_gen_or_i64(dest, t1, t0); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } static void gen_revh_d(TCGv dest, TCGv src1) @@ -171,9 +162,6 @@ static void gen_revh_d(TCGv dest, TCGv src1) tcg_gen_shli_tl(t0, t0, 16); tcg_gen_or_tl(t0, t0, t1); tcg_gen_rotri_tl(dest, t0, 32); - - tcg_temp_free(t0); - tcg_temp_free(t1); } static void gen_maskeqz(TCGv dest, TCGv src1, TCGv src2) diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/insn_trans/trans_fcmp.c.inc index 2ccf646ccb..3b0da2b9f4 100644 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc @@ -38,7 +38,6 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a) fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags)); tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); - tcg_temp_free(var); return true; } @@ -57,7 +56,5 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a) fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags)); tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); - - tcg_temp_free(var); return true; } diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc index 3025a1d3e9..0d11843873 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -13,12 +13,11 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop) static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) { TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp = NULL; CHECK_FPE; if (a->imm) { - temp = tcg_temp_new(); + TCGv temp = tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } @@ -26,31 +25,22 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); - if (temp) { - tcg_temp_free(temp); - } - return true; } static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) { TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp = NULL; CHECK_FPE; if (a->imm) { - temp = tcg_temp_new(); + TCGv temp = tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - - if (temp) { - tcg_temp_free(temp); - } return true; } @@ -66,7 +56,6 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); - tcg_temp_free(addr); return true; } @@ -82,7 +71,6 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop) addr = tcg_temp_new(); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - tcg_temp_free(addr); return true; } @@ -100,7 +88,6 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); - tcg_temp_free(addr); return true; } @@ -117,7 +104,6 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop) gen_helper_asrtgt_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - tcg_temp_free(addr); return true; } @@ -135,7 +121,6 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); - tcg_temp_free(addr); return true; } @@ -152,7 +137,6 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop) gen_helper_asrtle_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - tcg_temp_free(addr); return true; } diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc index 8e5106db4e..069c941665 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -18,7 +18,6 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a) tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero, cpu_fpr[a->fj], cpu_fpr[a->fk]); - tcg_temp_free(cond); return true; } @@ -82,9 +81,6 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a) tcg_gen_andi_i32(fcsr0, fcsr0, ~mask); tcg_gen_or_i32(fcsr0, fcsr0, temp); tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); - - tcg_temp_free_i32(temp); - tcg_temp_free_i32(fcsr0); } /* @@ -134,7 +130,6 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a) t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1); tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); - tcg_temp_free(t0); return true; } @@ -157,7 +152,6 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1); tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); - tcg_temp_free(t0); return true; } diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc index d5eb31147c..75cfdf59ad 100644 --- a/target/loongarch/insn_trans/trans_memory.c.inc +++ b/target/loongarch/insn_trans/trans_memory.c.inc @@ -7,21 +7,15 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp = NULL; if (a->imm) { - temp = tcg_temp_new(); + TCGv temp = tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); - - if (temp) { - tcg_temp_free(temp); - } - return true; } @@ -29,20 +23,14 @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop) { TCGv data = gpr_src(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp = NULL; if (a->imm) { - temp = tcg_temp_new(); + TCGv temp = tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); - - if (temp) { - tcg_temp_free(temp); - } - return true; } @@ -56,7 +44,6 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); - tcg_temp_free(addr); return true; } @@ -70,7 +57,6 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); - tcg_temp_free(addr); return true; } @@ -146,21 +132,15 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp = NULL; if (a->imm) { - temp = tcg_temp_new(); + TCGv temp = tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); - - if (temp) { - tcg_temp_free(temp); - } - return true; } @@ -168,20 +148,14 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop) { TCGv data = gpr_src(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp = NULL; if (a->imm) { - temp = tcg_temp_new(); + TCGv temp = tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr = temp; } tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); - - if (temp) { - tcg_temp_free(temp); - } - return true; } diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 56f4c45e09..5a04352b01 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -291,10 +291,6 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a) tcg_gen_st_tl(newv, cpu_env, csr->offset); } gen_set_gpr(a->rd, oldv, EXT_NONE); - - tcg_temp_free(temp); - tcg_temp_free(newv); - tcg_temp_free(oldv); return true; } diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/insn_trans/trans_shift.c.inc index 5260af2337..bf5428a2ba 100644 --- a/target/loongarch/insn_trans/trans_shift.c.inc +++ b/target/loongarch/insn_trans/trans_shift.c.inc @@ -8,7 +8,6 @@ static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x1f); tcg_gen_shl_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2) @@ -16,7 +15,6 @@ static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x1f); tcg_gen_shr_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2) @@ -24,7 +22,6 @@ static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x1f); tcg_gen_sar_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2) @@ -32,7 +29,6 @@ static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_shl_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2) @@ -40,7 +36,6 @@ static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_shr_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2) @@ -48,7 +43,6 @@ static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_sar_tl(dest, src1, t0); - tcg_temp_free(t0); } static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2) @@ -64,10 +58,6 @@ static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2) tcg_gen_rotr_i32(t1, t1, t2); tcg_gen_ext_i32_tl(dest, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free(t0); } static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2) @@ -75,7 +65,6 @@ static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 = tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_rotr_tl(dest, src1, t0); - tcg_temp_free(t0); } static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)

[PULL,42/84] target/loongarch: Drop tcg_temp_free

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Patch