diff mbox series

[PULL,13/62] target/arm: Remove `TARGET_TB_PCREL` define

Message ID	20230301025643.1227244-14-richard.henderson@linaro.org
State	Accepted
Commit	48fbcf5c6c630eb169a5f60b6a9f00ae2ae5de87
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Anton Johansson <anjo@rev.ng>, =?utf-8?q?Phili?= =?utf-8?q?ppe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 13/62] target/arm: Remove `TARGET_TB_PCREL` define Date: Tue, 28 Feb 2023 16:55:54 -1000 Message-Id: <20230301025643.1227244-14-richard.henderson@linaro.org> In-Reply-To: <20230301025643.1227244-1-richard.henderson@linaro.org> References: <20230301025643.1227244-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/62] exec/helper-head: Include missing "fpu/softfloat-types.h" header \| expand [PULL,01/62] exec/helper-head: Include missing "fpu/softfloat-types.h" header [PULL,02/62] softmmu: Use memmove in flatview_write_continue [PULL,03/62] accel/tcg: Add 'size' param to probe_access_flags() [PULL,04/62] accel/tcg: Add 'size' param to probe_access_full [PULL,05/62] include/exec: Introduce `CF_PCREL` [PULL,06/62] target/i386: set `CF_PCREL` in `x86_cpu_realizefn` [PULL,07/62] target/arm: set `CF_PCREL` in `arm_cpu_realizefn` [PULL,08/62] accel/tcg: Replace `TARGET_TB_PCREL` with `CF_PCREL` [PULL,09/62] include/exec: Replace `TARGET_TB_PCREL` with `CF_PCREL` [PULL,10/62] target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL` [PULL,11/62] target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL` [PULL,12/62] include/exec: Remove `TARGET_TB_PCREL` define [PULL,13/62] target/arm: Remove `TARGET_TB_PCREL` define [PULL,14/62] target/i386: Remove `TARGET_TB_PCREL` define [PULL,15/62] accel/tcg: Move jmp-cache `CF_PCREL` checks to caller [PULL,16/62] accel/tcg: Replace `tb_pc()` with `tb->pc` [PULL,17/62] target/tricore: Replace `tb_pc()` with `tb->pc` [PULL,18/62] target/sparc: Replace `tb_pc()` with `tb->pc` [PULL,19/62] target/sh4: Replace `tb_pc()` with `tb->pc` [PULL,20/62] target/rx: Replace `tb_pc()` with `tb->pc` [PULL,21/62] target/riscv: Replace `tb_pc()` with `tb->pc` [PULL,22/62] target/openrisc: Replace `tb_pc()` with `tb->pc` [PULL,23/62] target/mips: Replace `tb_pc()` with `tb->pc` [PULL,24/62] target/microblaze: Replace `tb_pc()` with `tb->pc` [PULL,25/62] target/loongarch: Replace `tb_pc()` with `tb->pc` [PULL,26/62] target/i386: Replace `tb_pc()` with `tb->pc` [PULL,27/62] target/hppa: Replace `tb_pc()` with `tb->pc` [PULL,28/62] target/hexagon: Replace `tb_pc()` with `tb->pc` [PULL,29/62] target/avr: Replace `tb_pc()` with `tb->pc` [PULL,30/62] target/arm: Replace `tb_pc()` with `tb->pc` [PULL,31/62] include/exec: Remove `tb_pc()` [PULL,32/62] tcg: Adjust TCGContext.temps_in_use check [PULL,33/62] accel/tcg: Pass max_insn to gen_intermediate_code by pointer [PULL,34/62] accel/tcg: Use more accurate max_insns for tb_overflow [PULL,35/62] tcg: Remove branch-to-next regardless of reference count [PULL,36/62] tcg: Rename TEMP_LOCAL to TEMP_TB [PULL,37/62] tcg: Use noinline for major tcg_gen_code subroutines [PULL,38/62] tcg: Add liveness_pass_0 [PULL,39/62] tcg: Remove TEMP_NORMAL [PULL,40/62] tcg: Pass TCGTempKind to tcg_temp_new_internal [PULL,41/62] tcg: Use tcg_constant_i32 in tcg_gen_io_start [PULL,42/62] tcg: Add tcg_gen_movi_ptr [PULL,43/62] tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} [PULL,44/62] tcg: Use tcg_temp_ebb_new_* in tcg/ [PULL,45/62] tcg: Use tcg_constant_ptr in do_dup [PULL,46/62] accel/tcg/plugin: Use tcg_temp_ebb_* [PULL,47/62] accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers [PULL,48/62] tcg: Don't re-use TEMP_TB temporaries [PULL,49/62] tcg: Change default temp lifetime to TEMP_TB [PULL,50/62] target/arm: Drop copies in gen_sve_{ldr,str} [PULL,51/62] target/arm: Don't use tcg_temp_local_new_* [PULL,52/62] target/cris: Don't use tcg_temp_local_new [PULL,53/62] target/hexagon: Don't use tcg_temp_local_new_* [PULL,54/62] target/hexagon/idef-parser: Drop gen_tmp_local [PULL,55/62] target/hppa: Don't use tcg_temp_local_new [PULL,56/62] target/i386: Don't use tcg_temp_local_new [PULL,57/62] target/mips: Don't use tcg_temp_local_new [PULL,58/62] target/ppc: Don't use tcg_temp_local_new [PULL,59/62] target/xtensa: Don't use tcg_temp_local_new_* [PULL,60/62] exec/gen-icount: Don't use tcg_temp_local_new_i32 [PULL,61/62] tcg: Remove tcg_temp_local_new_, tcg_const_local_ [PULL,62/62] tcg: Update docs/devel/tcg-ops.rst for temporary changes

Commit Message

Richard Henderson March 1, 2023, 2:55 a.m. UTC

From: Anton Johansson via <qemu-devel@nongnu.org>

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230227135202.9710-10-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu-param.h | 2 --
 1 file changed, 2 deletions(-)

diff mbox series

Patch

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 53cac9c89b..b7bde18986 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -31,8 +31,6 @@ 
 # define TARGET_PAGE_BITS_VARY
 # define TARGET_PAGE_BITS_MIN  10
 
-# define TARGET_TB_PCREL 1
-
 /*
  * Cache the attrs and shareability fields from the page table entry.
  *