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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id 26-20020aa7921a000000b00592417157f2sm843114pfo.148.2023.02.25.01.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Feb 2023 01:20:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH 66/76] target/sparc: Drop get_temp_i32 Date: Fri, 24 Feb 2023 23:14:17 -1000 Message-Id: <20230225091427.1817156-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230225091427.1817156-1-richard.henderson@linaro.org> References: <20230225091427.1817156-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new_i32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/sparc/translate.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2b4af692f6..bdf464f802 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -84,8 +84,6 @@ typedef struct DisasContext { uint32_t cc_op; /* current CC operation */ sparc_def_t *def; - TCGv_i32 t32[3]; - int n_t32; #ifdef TARGET_SPARC64 int fprs_dirty; int asi; @@ -129,14 +127,6 @@ static int sign_extend(int x, int len) #define IS_IMM (insn & (1<<13)) -static inline TCGv_i32 get_temp_i32(DisasContext *dc) -{ - TCGv_i32 t; - assert(dc->n_t32 < ARRAY_SIZE(dc->t32)); - dc->t32[dc->n_t32++] = t = tcg_temp_new_i32(); - return t; -} - static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) { #if defined(TARGET_SPARC64) @@ -153,7 +143,7 @@ static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) /* floating point registers moves */ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) { - TCGv_i32 ret = get_temp_i32(dc); + TCGv_i32 ret = tcg_temp_new_i32(); if (src & 1) { tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); } else { @@ -175,7 +165,7 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) { - return get_temp_i32(dc); + return tcg_temp_new_i32(); } static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) @@ -5516,7 +5506,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; } #endif - cpu_dst_32 = get_temp_i32(dc); + cpu_dst_32 = tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, dc->mem_idx, MO_TEUL); gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32); @@ -5762,14 +5752,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_exception(dc, TT_NCP_INSN); goto egress; #endif - egress: - if (dc->n_t32 != 0) { - int i; - for (i = dc->n_t32 - 1; i >= 0; --i) { - tcg_temp_free_i32(dc->t32[i]); - } - dc->n_t32 = 0; - } + egress:; } static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)