| Message ID | 20230225091427.1817156-52-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg: Drop tcg_temp_free from translators | expand |
On 2/25/23 06:14, Richard Henderson wrote: > Translators are no longer required to free tcg temporaries, > therefore there's no need to record temps for later freeing. > Replace the few uses with tcg_temp_new_i64. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/translate.c | 24 ++++-------------------- > 1 file changed, 4 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index f9d5d1097e..273e566d66 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -106,9 +106,6 @@ typedef struct DisasContext { > TCGv zero; > /* Space for 3 operands plus 1 extra for address computation. */ > TCGv temp[4]; > - /* Space for 4 operands(1 dest and <=3 src) for float point computation */ > - TCGv_i64 ftemp[4]; > - uint8_t nftemp; > /* PointerMasking extension */ > bool pm_mask_enabled; > bool pm_base_enabled; > @@ -431,12 +428,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) > } > } > > -static TCGv_i64 ftemp_new(DisasContext *ctx) > -{ > - assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); > - return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); > -} > - > static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) > { > if (!ctx->cfg_ptr->ext_zfinx) { > @@ -450,7 +441,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) > case MXL_RV32: > #ifdef TARGET_RISCV32 > { > - TCGv_i64 t = ftemp_new(ctx); > + TCGv_i64 t = tcg_temp_new_i64(); > tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); > return t; > } > @@ -476,7 +467,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) > switch (get_xl(ctx)) { > case MXL_RV32: > { > - TCGv_i64 t = ftemp_new(ctx); > + TCGv_i64 t = tcg_temp_new_i64(); > tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); > return t; > } > @@ -496,12 +487,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) > } > > if (reg_num == 0) { > - return ftemp_new(ctx); > + return tcg_temp_new_i64(); > } > > switch (get_xl(ctx)) { > case MXL_RV32: > - return ftemp_new(ctx); > + return tcg_temp_new_i64(); > #ifdef TARGET_RISCV64 > case MXL_RV64: > return cpu_gpr[reg_num]; > @@ -1207,8 +1198,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->cs = cs; > ctx->ntemp = 0; > memset(ctx->temp, 0, sizeof(ctx->temp)); > - ctx->nftemp = 0; > - memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); > ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); > ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > @@ -1244,11 +1233,6 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > ctx->temp[i] = NULL; > } > ctx->ntemp = 0; > - for (i = ctx->nftemp - 1; i >= 0; --i) { > - tcg_temp_free_i64(ctx->ftemp[i]); > - ctx->ftemp[i] = NULL; > - } > - ctx->nftemp = 0; > > /* Only the first insn within a TB is allowed to cross a page boundary. */ > if (ctx->base.is_jmp == DISAS_NEXT) {
On 2023/2/25 17:14, Richard Henderson wrote: > Translators are no longer required to free tcg temporaries, > therefore there's no need to record temps for later freeing. > Replace the few uses with tcg_temp_new_i64. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> How about the temp_new? Regards, Weiwei Li > --- > target/riscv/translate.c | 24 ++++-------------------- > 1 file changed, 4 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index f9d5d1097e..273e566d66 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -106,9 +106,6 @@ typedef struct DisasContext { > TCGv zero; > /* Space for 3 operands plus 1 extra for address computation. */ > TCGv temp[4]; > - /* Space for 4 operands(1 dest and <=3 src) for float point computation */ > - TCGv_i64 ftemp[4]; > - uint8_t nftemp; > /* PointerMasking extension */ > bool pm_mask_enabled; > bool pm_base_enabled; > @@ -431,12 +428,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) > } > } > > -static TCGv_i64 ftemp_new(DisasContext *ctx) > -{ > - assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); > - return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); > -} > - > static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) > { > if (!ctx->cfg_ptr->ext_zfinx) { > @@ -450,7 +441,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) > case MXL_RV32: > #ifdef TARGET_RISCV32 > { > - TCGv_i64 t = ftemp_new(ctx); > + TCGv_i64 t = tcg_temp_new_i64(); > tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); > return t; > } > @@ -476,7 +467,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) > switch (get_xl(ctx)) { > case MXL_RV32: > { > - TCGv_i64 t = ftemp_new(ctx); > + TCGv_i64 t = tcg_temp_new_i64(); > tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); > return t; > } > @@ -496,12 +487,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) > } > > if (reg_num == 0) { > - return ftemp_new(ctx); > + return tcg_temp_new_i64(); > } > > switch (get_xl(ctx)) { > case MXL_RV32: > - return ftemp_new(ctx); > + return tcg_temp_new_i64(); > #ifdef TARGET_RISCV64 > case MXL_RV64: > return cpu_gpr[reg_num]; > @@ -1207,8 +1198,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->cs = cs; > ctx->ntemp = 0; > memset(ctx->temp, 0, sizeof(ctx->temp)); > - ctx->nftemp = 0; > - memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); > ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); > ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > @@ -1244,11 +1233,6 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > ctx->temp[i] = NULL; > } > ctx->ntemp = 0; > - for (i = ctx->nftemp - 1; i >= 0; --i) { > - tcg_temp_free_i64(ctx->ftemp[i]); > - ctx->ftemp[i] = NULL; > - } > - ctx->nftemp = 0; > > /* Only the first insn within a TB is allowed to cross a page boundary. */ > if (ctx->base.is_jmp == DISAS_NEXT) {
On 2023/2/25 17:14, Richard Henderson wrote: > Translators are no longer required to free tcg temporaries, > therefore there's no need to record temps for later freeing. > Replace the few uses with tcg_temp_new_i64. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Weiwei Li > --- > target/riscv/translate.c | 24 ++++-------------------- > 1 file changed, 4 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index f9d5d1097e..273e566d66 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -106,9 +106,6 @@ typedef struct DisasContext { > TCGv zero; > /* Space for 3 operands plus 1 extra for address computation. */ > TCGv temp[4]; > - /* Space for 4 operands(1 dest and <=3 src) for float point computation */ > - TCGv_i64 ftemp[4]; > - uint8_t nftemp; > /* PointerMasking extension */ > bool pm_mask_enabled; > bool pm_base_enabled; > @@ -431,12 +428,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) > } > } > > -static TCGv_i64 ftemp_new(DisasContext *ctx) > -{ > - assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); > - return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); > -} > - > static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) > { > if (!ctx->cfg_ptr->ext_zfinx) { > @@ -450,7 +441,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) > case MXL_RV32: > #ifdef TARGET_RISCV32 > { > - TCGv_i64 t = ftemp_new(ctx); > + TCGv_i64 t = tcg_temp_new_i64(); > tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); > return t; > } > @@ -476,7 +467,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) > switch (get_xl(ctx)) { > case MXL_RV32: > { > - TCGv_i64 t = ftemp_new(ctx); > + TCGv_i64 t = tcg_temp_new_i64(); > tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); > return t; > } > @@ -496,12 +487,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) > } > > if (reg_num == 0) { > - return ftemp_new(ctx); > + return tcg_temp_new_i64(); > } > > switch (get_xl(ctx)) { > case MXL_RV32: > - return ftemp_new(ctx); > + return tcg_temp_new_i64(); > #ifdef TARGET_RISCV64 > case MXL_RV64: > return cpu_gpr[reg_num]; > @@ -1207,8 +1198,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->cs = cs; > ctx->ntemp = 0; > memset(ctx->temp, 0, sizeof(ctx->temp)); > - ctx->nftemp = 0; > - memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); > ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); > ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); > @@ -1244,11 +1233,6 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > ctx->temp[i] = NULL; > } > ctx->ntemp = 0; > - for (i = ctx->nftemp - 1; i >= 0; --i) { > - tcg_temp_free_i64(ctx->ftemp[i]); > - ctx->ftemp[i] = NULL; > - } > - ctx->nftemp = 0; > > /* Only the first insn within a TB is allowed to cross a page boundary. */ > if (ctx->base.is_jmp == DISAS_NEXT) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f9d5d1097e..273e566d66 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -106,9 +106,6 @@ typedef struct DisasContext { TCGv zero; /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; - /* Space for 4 operands(1 dest and <=3 src) for float point computation */ - TCGv_i64 ftemp[4]; - uint8_t nftemp; /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; @@ -431,12 +428,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) } } -static TCGv_i64 ftemp_new(DisasContext *ctx) -{ - assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); - return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); -} - static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) { if (!ctx->cfg_ptr->ext_zfinx) { @@ -450,7 +441,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) case MXL_RV32: #ifdef TARGET_RISCV32 { - TCGv_i64 t = ftemp_new(ctx); + TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); return t; } @@ -476,7 +467,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) switch (get_xl(ctx)) { case MXL_RV32: { - TCGv_i64 t = ftemp_new(ctx); + TCGv_i64 t = tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); return t; } @@ -496,12 +487,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) } if (reg_num == 0) { - return ftemp_new(ctx); + return tcg_temp_new_i64(); } switch (get_xl(ctx)) { case MXL_RV32: - return ftemp_new(ctx); + return tcg_temp_new_i64(); #ifdef TARGET_RISCV64 case MXL_RV64: return cpu_gpr[reg_num]; @@ -1207,8 +1198,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->cs = cs; ctx->ntemp = 0; memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->nftemp = 0; - memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); @@ -1244,11 +1233,6 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) ctx->temp[i] = NULL; } ctx->ntemp = 0; - for (i = ctx->nftemp - 1; i >= 0; --i) { - tcg_temp_free_i64(ctx->ftemp[i]); - ctx->ftemp[i] = NULL; - } - ctx->nftemp = 0; /* Only the first insn within a TB is allowed to cross a page boundary. */ if (ctx->base.is_jmp == DISAS_NEXT) {
Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new_i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/translate.c | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-)