[v3,26/30] target/ppc: Don't use tcg_temp_local_new

Message ID	20230225085945.1798188-27-richard.henderson@linaro.org
State	Superseded
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Series	tcg: Simplify temporary usage \| expand [v3,00/30] tcg: Simplify temporary usage [v3,01/30] tcg: Adjust TCGContext.temps_in_use check [v3,02/30] accel/tcg: Pass max_insn to gen_intermediate_code by pointer [v3,03/30] accel/tcg: Use more accurate max_insns for tb_overflow [v3,04/30] tcg: Remove branch-to-next regardless of reference count [v3,05/30] tcg: Rename TEMP_LOCAL to TEMP_TB [v3,06/30] tcg: Use noinline for major tcg_gen_code subroutines [v3,07/30] tcg: Add liveness_pass_0 [v3,08/30] tcg: Remove TEMP_NORMAL [v3,09/30] tcg: Pass TCGTempKind to tcg_temp_new_internal [v3,10/30] tcg: Use tcg_constant_i32 in tcg_gen_io_start [v3,11/30] tcg: Add tcg_gen_movi_ptr [v3,12/30] tcg: Add tcg_temp_ebb_new_{i32,i64,ptr} [v3,13/30] tcg: Use tcg_temp_ebb_new_* in tcg/ [v3,14/30] tcg: Use tcg_constant_ptr in do_dup [v3,15/30] accel/tcg/plugin: Use tcg_temp_ebb_* [v3,16/30] accel/tcg/plugin: Tidy plugin_gen_disable_mem_helpers [v3,17/30] tcg: Don't re-use TEMP_TB temporaries [v3,18/30] tcg: Change default temp lifetime to TEMP_TB [v3,19/30] target/arm: Drop copies in gen_sve_{ldr,str} [v3,20/30] target/arm: Don't use tcg_temp_local_new_* [v3,21/30] target/cris: Don't use tcg_temp_local_new [v3,22/30] target/hexagon: Don't use tcg_temp_local_new_* [v3,23/30] target/hppa: Don't use tcg_temp_local_new [v3,24/30] target/i386: Don't use tcg_temp_local_new [v3,25/30] target/mips: Don't use tcg_temp_local_new [v3,26/30] target/ppc: Don't use tcg_temp_local_new [v3,27/30] target/xtensa: Don't use tcg_temp_local_new_* [v3,28/30] exec/gen-icount: Don't use tcg_temp_local_new_i32 [v3,29/30] tcg: Remove tcg_temp_local_new_, tcg_const_local_ [v3,30/30] tcg: Update docs/devel/tcg-ops.rst for temporary changes

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Subject: [PATCH v3 26/30] target/ppc: Don't use tcg_temp_local_new
Date: Fri, 24 Feb 2023 22:59:41 -1000
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Series

tcg: Simplify temporary usage | expand

Commit Message

Richard Henderson Feb. 25, 2023, 8:59 a.m. UTC

Since tcg_temp_new is now identical, use that.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/translate.c              | 6 +++---
 target/ppc/translate/spe-impl.c.inc | 8 ++++----
 target/ppc/translate/vmx-impl.c.inc | 4 ++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5fe6aa641e..2956021e89 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4415,7 +4415,7 @@  static void gen_bcond(DisasContext *ctx, int type)
     TCGv target;
 
     if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
-        target = tcg_temp_local_new();
+        target = tcg_temp_new();
         if (type == BCOND_CTR) {
             tcg_gen_mov_tl(target, cpu_ctr);
         } else if (type == BCOND_TAR) {
@@ -5594,8 +5594,8 @@  static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
 {
     TCGv t0, t1;
 
-    t0 = tcg_temp_local_new();
-    t1 = tcg_temp_local_new();
+    t0 = tcg_temp_new();
+    t1 = tcg_temp_new();
 
     switch (opc3 & 0x0D) {
     case 0x05:
diff --git a/target/ppc/translate/spe-impl.c.inc b/target/ppc/translate/spe-impl.c.inc
index 2e6e799a25..bd8963db2b 100644
--- a/target/ppc/translate/spe-impl.c.inc
+++ b/target/ppc/translate/spe-impl.c.inc
@@ -168,7 +168,7 @@  static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
-    TCGv_i32 t0 = tcg_temp_local_new_i32();
+    TCGv_i32 t0 = tcg_temp_new_i32();
 
     /* No error here: 6 bits are used */
     tcg_gen_andi_i32(t0, arg2, 0x3F);
@@ -185,7 +185,7 @@  static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
-    TCGv_i32 t0 = tcg_temp_local_new_i32();
+    TCGv_i32 t0 = tcg_temp_new_i32();
 
     /* No error here: 6 bits are used */
     tcg_gen_andi_i32(t0, arg2, 0x3F);
@@ -202,7 +202,7 @@  static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
-    TCGv_i32 t0 = tcg_temp_local_new_i32();
+    TCGv_i32 t0 = tcg_temp_new_i32();
 
     /* No error here: 6 bits are used */
     tcg_gen_andi_i32(t0, arg2, 0x3F);
@@ -378,7 +378,7 @@  static inline void gen_evsel(DisasContext *ctx)
     TCGLabel *l2 = gen_new_label();
     TCGLabel *l3 = gen_new_label();
     TCGLabel *l4 = gen_new_label();
-    TCGv_i32 t0 = tcg_temp_local_new_i32();
+    TCGv_i32 t0 = tcg_temp_new_i32();
 
     tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
     tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 7741f2eb49..2dd17ab106 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1508,8 +1508,8 @@  static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
     REQUIRE_INSNS_FLAGS2(ctx, ISA310);
     REQUIRE_VECTOR(ctx);
 
-    vra = tcg_temp_local_new_i64();
-    vrb = tcg_temp_local_new_i64();
+    vra = tcg_temp_new_i64();
+    vrb = tcg_temp_new_i64();
     gt = gen_new_label();
     lt = gen_new_label();
     done = gen_new_label();

[v3,26/30] target/ppc: Don't use tcg_temp_local_new

Commit Message

Patch