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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id i25-20020aa79099000000b005810a54fdefsm79051pfa.114.2023.02.15.19.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 19:09:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v1 02/19] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP Date: Wed, 15 Feb 2023 17:08:37 -1000 Message-Id: <20230216030854.1212208-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216030854.1212208-1-richard.henderson@linaro.org> References: <20230216030854.1212208-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While we don't require 16-byte atomicity here, using a single larger load simplifies the code, and makes it a closer match to STXP. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 78a2141224..d7d4b68328 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2545,30 +2545,27 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); } } else { - /* The pair must be single-copy atomic for *each* doubleword, not - the entire quadword, however it must be quadword aligned. */ - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); + /* + * The pair must be single-copy atomic for *each* doubleword, not + * the entire quadword, however it must be quadword aligned. + * Expose the complete load to tcg, for ease of tlb lookup, + * but indicate that only 8-byte atomicity is required. + */ + TCGv_i128 t16 = tcg_temp_new_i128(); - memop |= MO_64; - tcg_gen_qemu_ld_i64(t0, addr, idx, memop | MO_ALIGN_16); + memop |= MO_128 | MO_ALIGN_16 | MO_ATMAX_8; + tcg_gen_qemu_ld_i128(t16, addr, idx, memop); - tcg_gen_addi_i64(t1, addr, 8); - tcg_gen_qemu_ld_i64(t1, t1, idx, memop); + tcg_gen_extr_i128_i64(cpu_exclusive_val, cpu_exclusive_high, t16); + tcg_temp_free_i128(t16); if (s->be_data == MO_LE) { - tcg_gen_mov_i64(cpu_exclusive_val, t0); - tcg_gen_mov_i64(cpu_exclusive_high, t1); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); } else { - tcg_gen_mov_i64(cpu_exclusive_high, t0); - tcg_gen_mov_i64(cpu_exclusive_val, t1); + tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_high); + tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_val); } - - tcg_gen_mov_i64(cpu_reg(s, rt), t0); - tcg_gen_mov_i64(cpu_reg(s, rt2), t1); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } } else { memop |= size | MO_ALIGN;