From patchwork Thu Feb 16 02:57:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 653967 Delivered-To: patch@linaro.org Received: by 2002:adf:f90f:0:0:0:0:0 with SMTP id b15csp118666wrr; Wed, 15 Feb 2023 18:59:43 -0800 (PST) X-Google-Smtp-Source: AK7set8M2h4OLZHlEhkE/AOePJ/CiE/CLxs1EjoOSdg1G0gsnPB+3X2wzYYNsQXWXpQTa0qJtUrb X-Received: by 2002:ac8:7f91:0:b0:3ba:3ac7:ccf1 with SMTP id z17-20020ac87f91000000b003ba3ac7ccf1mr7325774qtj.58.1676516382919; Wed, 15 Feb 2023 18:59:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676516382; cv=none; d=google.com; s=arc-20160816; b=EdDe3eZYY7P8TWVHlxiizcygIM+tvRL6GDvRHHQC9H9xiOtSfoQ2mTC14AV4QEVzU6 vCjrTX2E9EObqRoy8Dmc1ZHgv9ls5h4zh21bPW3Pgo0itK7XVs9TnAnJv4DsS5RJKiUp Rh7EjXrTNwqpuo3B5LXvZU0zKC6/WIvMn0RHfagfpwbib9gxIVoKmuD7ceKqnihndj58 zE2pKOgYm/COXYcFQ7DyOftxoTwEU01kgLl+ux3Mle0GUpWpcpCos/+SGRLFnq6FAZJ9 zABduEU1MCfHoK0yBF2OQk30lAKqj0rePu+Utwtha4yit4sp9QCIgHDYztUqacXKT/kb geVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QP+/EHiQKRHx1fO7mLC4dIgIU6Ym3+F7e4Wu/m2d1pQ=; b=EFjbHVnctrzutmRlfa8Ug5LreMurIDX5YZ/7S5zb2T4NPfXtOCTfJXFLzW8qKYXR4d +XwnoS4b2rSSdO9CN3nkUinzpuJsVscvJX7O34N777ouUySaDx9tzQkH0f0jGZUf9Zce 1rJVa6HeSpgqL4676a9+UOqXSbs7BJ6C5QoCACHshBOfFMgTA2rqQAbkR4XThxhfb/RK Fj3wa/NP5CkJwUW4pLjPPS86uK9mSZCJtf6QW3o/sH1Xt0vDq/3tpb3a214d+9x3n9mB Z6JMoLGvPBWnicx67sSXKsOh9nyOQPA7dYO7wgUd4YYuzf+geG5G8cFI/yinqH5RdVi+ Hryg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i9OR7AVN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 1-20020ac85941000000b003bcdd210467si503858qtz.379.2023.02.15.18.59.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Feb 2023 18:59:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i9OR7AVN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pSUTH-0003VD-RU; Wed, 15 Feb 2023 21:58:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pSUTE-0003T0-OP for qemu-devel@nongnu.org; Wed, 15 Feb 2023 21:58:04 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pSUTC-0005ka-Np for qemu-devel@nongnu.org; Wed, 15 Feb 2023 21:58:04 -0500 Received: by mail-pf1-x441.google.com with SMTP id bw10so617576pfb.0 for ; Wed, 15 Feb 2023 18:58:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QP+/EHiQKRHx1fO7mLC4dIgIU6Ym3+F7e4Wu/m2d1pQ=; b=i9OR7AVN0KsuyYPTZnRm2cIoFPcpmpTQ70AER6hKsFGo0Wf5neh+dR2swaZpa/MS6I VF44WqvDjWH7WEqTSSckMhYb45hn7QWePMMZvgegfRk1k15lrFtPPQMfzrvGL8WXF+nc KYyaWzcedxnDyFnHKMPcl1Nnd2xSZDkS80tpAyoQN/PfzYGjA4J5I7rqYRv/FngxMPnc bw/7pKnplqjDEYDN57hhbh+SL5+hbo0DDtIuqZ0w2jdfLg9oLwyOpJcfTOqN/cVyCsOL 7WJ9zf+d2OEgkMy81RlooJu/YfQ12HRefCAKI0gdnQktX51p9p6gI+A6/dI1cwwsvQZk Xtjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QP+/EHiQKRHx1fO7mLC4dIgIU6Ym3+F7e4Wu/m2d1pQ=; b=SvFwiZiD0RImmk/Zn5BWUxUmpD86NEjIs+DZU/ofFF4UCyTPwsSlkHd+ei0mvQc/6U FnL28TM+L9LEiXjB0W5MI8BXvK8kyQdRK28iyAFaEK6Evrk4/kC6rn3cScPXU5MlShFo gL8WA+gXLYUr/Pgiz7NgOndiZTyuhU8SY/a4CyrI8hzPkq8OvilkRpEszBUlAF2DpfvT baQQvJjqxH6eEG9mKsEoiCaMwsV4PU0+HrKWMHNUtINAnRmspT+QXyNBSJ3xLUDWcGGd /YrYhy4PEcfQab8xDtgrG1q2GTcwNh5mW89g4v0qZxM82ZYbX37tdoi+DTuPCHh4EEof nwQw== X-Gm-Message-State: AO0yUKUwvRHjwhHLyTgnQ++r6rkHUh2gZIVU/V7orpFiF2wzf7rMEX5J I8WyJxzylaETouqUqVSkUVrTJwYlMSUrKiP55oZOnQ== X-Received: by 2002:aa7:8428:0:b0:5a8:bbac:1cf2 with SMTP id q8-20020aa78428000000b005a8bbac1cf2mr3574334pfn.1.1676516281304; Wed, 15 Feb 2023 18:58:01 -0800 (PST) Received: from stoup.. (rrcs-74-87-59-234.west.biz.rr.com. [74.87.59.234]) by smtp.gmail.com with ESMTPSA id e14-20020a62aa0e000000b005a816b7c3e8sm89655pff.24.2023.02.15.18.58.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 18:58:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/30] tcg/i386: Add have_atomic16 Date: Wed, 15 Feb 2023 16:57:23 -1000 Message-Id: <20230216025739.1211680-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230216025739.1211680-1-richard.henderson@linaro.org> References: <20230216025739.1211680-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Notice when Intel or AMD have guaranteed that vmovdqa is atomic. The new variable will also be used in generated code. Signed-off-by: Richard Henderson --- include/qemu/cpuid.h | 18 ++++++++++++++++++ tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.c.inc | 27 +++++++++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h index 1451e8ef2f..35325f1995 100644 --- a/include/qemu/cpuid.h +++ b/include/qemu/cpuid.h @@ -71,6 +71,24 @@ #define bit_LZCNT (1 << 5) #endif +/* + * Signatures for different CPU implementations as returned from Leaf 0. + */ + +#ifndef signature_INTEL_ecx +/* "Genu" "ineI" "ntel" */ +#define signature_INTEL_ebx 0x756e6547 +#define signature_INTEL_edx 0x49656e69 +#define signature_INTEL_ecx 0x6c65746e +#endif + +#ifndef signature_AMD_ecx +/* "Auth" "enti" "cAMD" */ +#define signature_AMD_ebx 0x68747541 +#define signature_AMD_edx 0x69746e65 +#define signature_AMD_ecx 0x444d4163 +#endif + static inline unsigned xgetbv_low(unsigned c) { unsigned a, d; diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index d4f2a6f8c2..0421776cb8 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -120,6 +120,7 @@ extern bool have_avx512dq; extern bool have_avx512vbmi2; extern bool have_avx512vl; extern bool have_movbe; +extern bool have_atomic16; /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 29dba3fa1c..977650263b 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -185,6 +185,7 @@ bool have_avx512dq; bool have_avx512vbmi2; bool have_avx512vl; bool have_movbe; +bool have_atomic16; #ifdef CONFIG_CPUID_H static bool have_bmi2; @@ -4173,6 +4174,32 @@ static void tcg_target_init(TCGContext *s) have_avx512dq = (b7 & bit_AVX512DQ) != 0; have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0; } + + /* + * The Intel SDM has added: + * Processors that enumerate support for Intel® AVX + * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28]) + * guarantee that the 16-byte memory operations performed + * by the following instructions will always be carried + * out atomically: + * - MOVAPD, MOVAPS, and MOVDQA. + * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128. + * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded + * with EVEX.128 and k0 (masking disabled). + * Note that these instructions require the linear addresses + * of their memory operands to be 16-byte aligned. + * + * AMD has provided an even stronger guarantee that processors + * with AVX provide 16-byte atomicity for all cachable, + * naturally aligned single loads and stores, e.g. MOVDQU. + * + * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 + */ + if (have_avx1) { + __cpuid(0, a, b, c, d); + have_atomic16 = (c == signature_INTEL_ecx || + c == signature_AMD_ecx); + } } } }