From patchwork Fri Feb 3 18:09:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 650096 Delivered-To: patch@linaro.org Received: by 2002:a17:522:d8c:b0:4be:c3dc:14d8 with SMTP id d12csp971747pva; Fri, 3 Feb 2023 10:11:06 -0800 (PST) X-Google-Smtp-Source: AK7set9Wv42a5uOnttPTLUgItQk7lfR6fo3Es+7isLGIuiwCsURMjuYLVan/pSxgWiPpcGd+5vYG X-Received: by 2002:a05:6214:1191:b0:537:791f:48e5 with SMTP id t17-20020a056214119100b00537791f48e5mr16303611qvv.22.1675447865923; Fri, 03 Feb 2023 10:11:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675447865; cv=none; d=google.com; s=arc-20160816; b=wUZhD7zKiBk5xH1oG4kFDtaUrafbv9l6u3Ic79/07ZX4B+efkL0AtbVoF86GdYxfXE z+kcS6eEN6BEBf7fgvaFAz/30oUxYHwFurlBBsLNRSIFMctgf29FTSy0TrSscF7YZZ5H myV/Lflm6mwh4zwTO0wF7tae6s/Guyp0G1AFqbYUCXwypAOaC4CGZjKwZnMWZMy8B+bb Tz04KERri141vNf6KmTkti3fOJHpRWEZLi1MXaCQjtQbZZOgeukkkv6yFfIcJQLez/8y jOxuQDGrqd69rzbEsKYHmZEDDgGgeymCkRbS2jXf0TALtWaDsONow+jB6qUYqbL2f0Sx spVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SLTcZ2bERqFx5QJrSflHdKK5QKRI/+byta3hYLUUz0c=; b=UaQqQkUH+Ynzqyg22uqVeCoOVDRUPPwvt566/ythtf1+PiSEc6B/uBcek1hmcg/1T+ Gc4ujCwsBneQ32EDi98F0zwqjm4bzfbsGN6eMn+EHya4XtG7rYUL+2bIHrwY+hCCjxfe foSAk2tOYq/JHXWfgTRMZ6/Q0O3A1ux/pp4D98eM4BFZ5zimY/QSayPjQcChbGwIBIwI Nmmjhp9TtCEEA+So8m1KSeyo04JCWi8IaRrSFzy5uAx5WJFM3vGI558JnJkY5hMRhC6R d/GyqzetmiRmzqI7LbTF8e1LdVGMOatx4hjgzW4cVSgH7woTz2/dcDRd0ridMzwa0ZkV wWWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zvZlsVJv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u14-20020ad45aae000000b005351bff5a00si2601313qvg.238.2023.02.03.10.11.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Feb 2023 10:11:05 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zvZlsVJv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pO0WF-0001x9-Uh; Fri, 03 Feb 2023 13:10:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pO0WD-0001nI-Vl for qemu-devel@nongnu.org; Fri, 03 Feb 2023 13:10:38 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pO0WC-0000DK-3K for qemu-devel@nongnu.org; Fri, 03 Feb 2023 13:10:37 -0500 Received: by mail-wm1-x32c.google.com with SMTP id bg26so4526878wmb.0 for ; Fri, 03 Feb 2023 10:10:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SLTcZ2bERqFx5QJrSflHdKK5QKRI/+byta3hYLUUz0c=; b=zvZlsVJvQ9nVYz40xbEJsOTsWOExXlNi5m+ZWR11e2QgZdOlbijtW1EZV+9yYyttom qx/cONN4L24gJJ/b5iMak+z+CGG4sjTGq8RJDVKQlXkUFeP7es8lB3xKokC9GcBTVLyl seplGESIzoWOj+ioKMB/V9KcRLoilrWM069r/uvImip8xqqtk+ss1DhVGJrR9RYaZGp3 6GOe+Iq1VClsXRp+I1Uj4H3Y1hgXzAGWQKsZIscAtis+Q9rVXioUMnPgzpM5/evUAJmC EfrMEr6vLAys23XdlDl6QPEuhQCMmnjNdo65f/xcUID3GvN8axykf9Th2xh5KR/YY5O5 nzvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SLTcZ2bERqFx5QJrSflHdKK5QKRI/+byta3hYLUUz0c=; b=7lWs+twxjGoZa1IIF07eUIZjlYQJK2coP1JCNIPtZRtlvbw3xWRQhLxmQrtUxZsE33 Il2fvpXTpo1lIJvTVFXG3xvj82ZmKvcOCbm7LIP7mze9/CpYCCli6WbZdHd5XYAcLmB0 cN2WMrU6/0j0WJQeu963XmC+pZCaJN3yva70MOD+9PPneSfMRPSBjjrHWeIaQGx7Dcdn SaVR4QsfDuq3g5OjLFqidtt1POlc0wndLruGXDQQNLdRgLAKNpGM9rgqff3843ltqcn0 AODIz1qNAgi57kgVKq84gCjX0ZvQH+0CZB+bAvr+7QoS4hnllMXmHDPzmaCVymncxqSg FvWA== X-Gm-Message-State: AO0yUKWE9BP9zIuhNyDd8Y+4Ja8Cds43x/qidpEvlNmX7C5fPZiuoJs4 NTCSkarzHNSHwHO6AwxmHtSGmOUPkr60L5QJ X-Received: by 2002:a05:600c:35c6:b0:3de:56a8:ae6b with SMTP id r6-20020a05600c35c600b003de56a8ae6bmr4915919wmq.34.1675447835110; Fri, 03 Feb 2023 10:10:35 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id m2-20020a05600c4f4200b003dc522dd25esm3702947wmq.30.2023.02.03.10.10.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 Feb 2023 10:10:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Markus Armbruster , Eduardo Habkost , qemu-riscv@nongnu.org, =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= , Paul Burton , Aleksandar Rikalo , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= , Aurelien Jarno , Jiaxun Yang Subject: [RFC PATCH 15/19] hw/mips: Set QDev properties using QDev API Date: Fri, 3 Feb 2023 19:09:10 +0100 Message-Id: <20230203180914.49112-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230203180914.49112-1-philmd@linaro.org> References: <20230203180914.49112-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to use the low-level QOM API when an object inherits from QDev. Directly use the QDev API to set its properties. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 6 ++---- hw/mips/cps.c | 42 ++++++++++++++---------------------------- hw/mips/jazz.c | 3 +-- hw/mips/malta.c | 6 ++---- 4 files changed, 19 insertions(+), 38 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 21ad844519..f3c2179f66 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -700,10 +700,8 @@ static void boston_mach_init(MachineState *machine) } object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); - object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, - &error_fatal); - object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, - &error_fatal); + qdev_prop_set_string(DEVICE(&s->cps), "cpu-type", machine->cpu_type); + qdev_prop_set_uint32(DEVICE(&s->cps), "num-vp", machine->smp.cpus); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", qdev_get_clock_out(dev, "cpu-refclk")); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 2b5269ebf1..3109644c5e 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -79,10 +79,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) CPUMIPSState *env = &cpu->env; /* All VPs are halted on reset. Leave powering up to CPC. */ - if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true, - errp)) { - return; - } + qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", true); + /* All cores use the same clock tree */ qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock); @@ -106,12 +104,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); - object_property_set_link(OBJECT(&s->itu), "cpu[0]", - OBJECT(first_cpu), &error_abort); - object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, - &error_abort); - object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, - &error_abort); + qdev_prop_set_link(DEVICE(&s->itu), "cpu[0]", OBJECT(first_cpu)); + qdev_prop_set_uint32(DEVICE(&s->itu), "num-fifo", 16); + qdev_prop_set_uint32(DEVICE(&s->itu), "num-semaphores", 16); if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { return; } @@ -122,10 +117,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Cluster Power Controller */ object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); - object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, - &error_abort); - object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, - &error_abort); + qdev_prop_set_uint32(DEVICE(&s->cpc), "num-vp", s->num_vp); + qdev_prop_set_uint64(DEVICE(&s->cpc), "vp-start-running", 0x1); if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) { return; } @@ -135,10 +128,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) /* Global Interrupt Controller */ object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); - object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp, - &error_abort); - object_property_set_uint(OBJECT(&s->gic), "num-irq", 128, - &error_abort); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-vp", s->num_vp); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", 128); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { return; } @@ -150,16 +141,11 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); - object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, - &error_abort); - object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, - &error_abort); - object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, - &error_abort); - object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), - &error_abort); - object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), - &error_abort); + qdev_prop_set_uint32(DEVICE(&s->gcr), "num-vp", s->num_vp); + qdev_prop_set_int32(DEVICE(&s->gcr), "gcr-rev", 0x800); + qdev_prop_set_uint64(DEVICE(&s->gcr), "gcr-base", gcr_base); + qdev_prop_set_link(DEVICE(&s->gcr), "gic", OBJECT(&s->gic.mr)); + qdev_prop_set_link(DEVICE(&s->gcr), "cpc", OBJECT(&s->cpc.mr)); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { return; } diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 6aefe9a61b..d18aeb439b 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -302,8 +302,7 @@ static void mips_jazz_init(MachineState *machine, qdev_set_nic_properties(dev, nd); qdev_prop_set_uint8(dev, "it_shift", 2); qdev_prop_set_bit(dev, "big_endian", big_endian > 0); - object_property_set_link(OBJECT(dev), "dma_mr", - OBJECT(rc4030_dma_mr), &error_abort); + qdev_prop_set_link(dev, "dma_mr", OBJECT(rc4030_dma_mr)); sysbus = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sysbus, &error_fatal); sysbus_mmio_map(sysbus, 0, 0x80001000); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index af9021316d..3b88668bae 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1064,10 +1064,8 @@ static void create_cps(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); - object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, - &error_fatal); - object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, - &error_fatal); + qdev_prop_set_string(DEVICE(&s->cps), "cpu-type", ms->cpu_type); + qdev_prop_set_uint32(DEVICE(&s->cps), "num-vp", ms->smp.cpus); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);