| Message ID | 20230203113650.78146-10-philmd@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | hw: Use QOM alias properties and few QOM/QDev cleanups | expand |
> 2023年2月3日 11:36，Philippe Mathieu-Daudé <philmd@linaro.org> 写道： > > QOM objects shouldn't access each other internals fields > except using the QOM API. > > mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and > directly sets the 'saar' pointer: > > if (saar_present) { > s->itu.saar = &env->CP0_SAAR; > } > > In order to avoid that, pass the MIPS_CPU object via a QOM > link property, and set the 'saar' pointer in mips_itu_realize(). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested with ITU cases. > --- > RFC because not tested. > --- > hw/mips/cps.c | 23 ++++++----------------- > hw/misc/mips_itu.c | 26 ++++++++++++++++++-------- > include/hw/misc/mips_itu.h | 5 ++--- > 3 files changed, 26 insertions(+), 28 deletions(-) > > diff --git a/hw/mips/cps.c b/hw/mips/cps.c > index 38acc57468..2b5269ebf1 100644 > --- a/hw/mips/cps.c > +++ b/hw/mips/cps.c > @@ -66,20 +66,17 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env) > static void mips_cps_realize(DeviceState *dev, Error **errp) > { > MIPSCPSState *s = MIPS_CPS(dev); > - CPUMIPSState *env; > - MIPSCPU *cpu; > - int i; > target_ulong gcr_base; > bool itu_present = false; > - bool saar_present = false; > > if (!clock_get(s->clock)) { > error_setg(errp, "CPS input clock is not connected to an output clock"); > return; > } > > - for (i = 0; i < s->num_vp; i++) { > - cpu = MIPS_CPU(object_new(s->cpu_type)); > + for (int i = 0; i < s->num_vp; i++) { > + MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); > + CPUMIPSState *env = &cpu->env; > > /* All VPs are halted on reset. Leave powering up to CPC. */ > if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true, > @@ -97,7 +94,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) > cpu_mips_irq_init_cpu(cpu); > cpu_mips_clock_init(cpu); > > - env = &cpu->env; > if (cpu_mips_itu_supported(env)) { > itu_present = true; > /* Attach ITC Tag to the VP */ > @@ -107,22 +103,15 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) > qemu_register_reset(main_cpu_reset, cpu); > } > > - cpu = MIPS_CPU(first_cpu); > - env = &cpu->env; > - saar_present = (bool)env->saarp; > - > /* Inter-Thread Communication Unit */ > if (itu_present) { > object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); > + object_property_set_link(OBJECT(&s->itu), "cpu[0]", > + OBJECT(first_cpu), &error_abort); > object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, > &error_abort); > object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, > &error_abort); > - object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present, > - &error_abort); > - if (saar_present) { > - s->itu.saar = &env->CP0_SAAR; > - } > if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { > return; > } > @@ -158,7 +147,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) > sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); > > /* Global Configuration Registers */ > - gcr_base = env->CP0_CMGCRBase << 4; > + gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; > > object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); > object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, > diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c > index a06cdd10ea..0eda302db4 100644 > --- a/hw/misc/mips_itu.c > +++ b/hw/misc/mips_itu.c > @@ -93,10 +93,10 @@ void itc_reconfigure(MIPSITUState *tag) > uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); > bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; > > - if (tag->saar_present) { > - address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; > - size = 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f); > - is_enabled = *(uint64_t *) tag->saar & 1; > + if (tag->saar) { > + address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; > + size = 1ULL << ((tag->saar[0] >> 1) & 0x1f); > + is_enabled = tag->saar[0] & 1; > } > > memory_region_transaction_begin(); > @@ -157,7 +157,7 @@ static inline ITCView get_itc_view(hwaddr addr) > static inline int get_cell_stride_shift(const MIPSITUState *s) > { > /* Minimum interval (for EntryGain = 0) is 128 B */ > - if (s->saar_present) { > + if (s->saar) { > return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & > ITC_ICR0_BLK_GRAIN_MASK); > } else { > @@ -515,6 +515,7 @@ static void mips_itu_init(Object *obj) > static void mips_itu_realize(DeviceState *dev, Error **errp) > { > MIPSITUState *s = MIPS_ITU(dev); > + CPUMIPSState *env; > > if (s->num_fifo > ITC_FIFO_NUM_MAX) { > error_setg(errp, "Exceed maximum number of FIFO cells: %d", > @@ -526,6 +527,15 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) > s->num_semaphores); > return; > } > + if (!s->cpu0) { > + error_setg(errp, "Missing 'cpu[0]' property"); > + return; > + } > + > + env = &s->cpu0->env; > + if (env->saarp) { > + s->saar = env->CP0_SAAR; > + } > > s->cell = g_new(ITCStorageCell, get_num_cells(s)); > } > @@ -534,8 +544,8 @@ static void mips_itu_reset(DeviceState *dev) > { > MIPSITUState *s = MIPS_ITU(dev); > > - if (s->saar_present) { > - *(uint64_t *) s->saar = 0x11 << 1; > + if (s->saar) { > + s->saar[0] = 0x11 << 1; > s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM; > } else { > s->ITCAddressMap[0] = 0; > @@ -553,7 +563,7 @@ static Property mips_itu_properties[] = { > ITC_FIFO_NUM_MAX), > DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, > ITC_SEMAPH_NUM_MAX), > - DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), > + DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU *), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h > index ab6d286c38..35218b2d14 100644 > --- a/include/hw/misc/mips_itu.h > +++ b/include/hw/misc/mips_itu.h > @@ -72,9 +72,8 @@ struct MIPSITUState { > uint64_t icr0; > > /* SAAR */ > - bool saar_present; > - void *saar; > - > + uint64_t *saar; > + MIPSCPU *cpu0; > }; > > /* Get ITC Configuration Tag memory region. */ > -- > 2.38.1 >
diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 38acc57468..2b5269ebf1 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -66,20 +66,17 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env) static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s = MIPS_CPS(dev); - CPUMIPSState *env; - MIPSCPU *cpu; - int i; target_ulong gcr_base; bool itu_present = false; - bool saar_present = false; if (!clock_get(s->clock)) { error_setg(errp, "CPS input clock is not connected to an output clock"); return; } - for (i = 0; i < s->num_vp; i++) { - cpu = MIPS_CPU(object_new(s->cpu_type)); + for (int i = 0; i < s->num_vp; i++) { + MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type)); + CPUMIPSState *env = &cpu->env; /* All VPs are halted on reset. Leave powering up to CPC. */ if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true, @@ -97,7 +94,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); - env = &cpu->env; if (cpu_mips_itu_supported(env)) { itu_present = true; /* Attach ITC Tag to the VP */ @@ -107,22 +103,15 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) qemu_register_reset(main_cpu_reset, cpu); } - cpu = MIPS_CPU(first_cpu); - env = &cpu->env; - saar_present = (bool)env->saarp; - /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); + object_property_set_link(OBJECT(&s->itu), "cpu[0]", + OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, &error_abort); - object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present, - &error_abort); - if (saar_present) { - s->itu.saar = &env->CP0_SAAR; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { return; } @@ -158,7 +147,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); /* Global Configuration Registers */ - gcr_base = env->CP0_CMGCRBase << 4; + gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index a06cdd10ea..0eda302db4 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -93,10 +93,10 @@ void itc_reconfigure(MIPSITUState *tag) uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; - if (tag->saar_present) { - address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; - size = 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f); - is_enabled = *(uint64_t *) tag->saar & 1; + if (tag->saar) { + address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; + size = 1ULL << ((tag->saar[0] >> 1) & 0x1f); + is_enabled = tag->saar[0] & 1; } memory_region_transaction_begin(); @@ -157,7 +157,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain = 0) is 128 B */ - if (s->saar_present) { + if (s->saar) { return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & ITC_ICR0_BLK_GRAIN_MASK); } else { @@ -515,6 +515,7 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s = MIPS_ITU(dev); + CPUMIPSState *env; if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -526,6 +527,15 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) s->num_semaphores); return; } + if (!s->cpu0) { + error_setg(errp, "Missing 'cpu[0]' property"); + return; + } + + env = &s->cpu0->env; + if (env->saarp) { + s->saar = env->CP0_SAAR; + } s->cell = g_new(ITCStorageCell, get_num_cells(s)); } @@ -534,8 +544,8 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s = MIPS_ITU(dev); - if (s->saar_present) { - *(uint64_t *) s->saar = 0x11 << 1; + if (s->saar) { + s->saar[0] = 0x11 << 1; s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM; } else { s->ITCAddressMap[0] = 0; @@ -553,7 +563,7 @@ static Property mips_itu_properties[] = { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), + DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index ab6d286c38..35218b2d14 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -72,9 +72,8 @@ struct MIPSITUState { uint64_t icr0; /* SAAR */ - bool saar_present; - void *saar; - + uint64_t *saar; + MIPSCPU *cpu0; }; /* Get ITC Configuration Tag memory region. */
QOM objects shouldn't access each other internals fields except using the QOM API. mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and directly sets the 'saar' pointer: if (saar_present) { s->itu.saar = &env->CP0_SAAR; } In order to avoid that, pass the MIPS_CPU object via a QOM link property, and set the 'saar' pointer in mips_itu_realize(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- RFC because not tested. --- hw/mips/cps.c | 23 ++++++----------------- hw/misc/mips_itu.c | 26 ++++++++++++++++++-------- include/hw/misc/mips_itu.h | 5 ++--- 3 files changed, 26 insertions(+), 28 deletions(-)