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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id b4-20020a17090a7ac400b0022c35afad5bsm2496763pjl.16.2023.02.01.23.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 23:52:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: anders.roxell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 2/4] target/arm: Store tbi for both insns and data in ARMVAParameters Date: Wed, 1 Feb 2023 21:52:40 -1000 Message-Id: <20230202075242.260793-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202075242.260793-1-richard.henderson@linaro.org> References: <20230202075242.260793-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is slightly more work on the consumer side, but means we will be able to compute this once for multiple uses. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 5 +++-- target/arm/helper.c | 18 +++++++++--------- target/arm/pauth_helper.c | 29 ++++++++++++++++------------- target/arm/ptw.c | 6 +++--- 4 files changed, 31 insertions(+), 27 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d9555309df..73b37478bf 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1072,7 +1072,8 @@ typedef struct ARMVAParameters { unsigned ps : 3; unsigned sh : 2; unsigned select : 1; - bool tbi : 1; + bool tbid : 1; /* final TBI for data, not the TBID field */ + bool tbii : 1; /* final TBI for insns */ bool epd : 1; bool hpd : 1; bool tsz_oob : 1; /* tsz has been clamped to legal range */ @@ -1083,7 +1084,7 @@ typedef struct ARMVAParameters { } ARMVAParameters; ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data); + ARMMMUIdx mmu_idx); int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); diff --git a/target/arm/helper.c b/target/arm/helper.c index 8ad9a667f1..fda0b9da75 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4874,7 +4874,7 @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, unsigned int page_size_granule, page_shift, num, scale, exponent; /* Extract one bit to represent the va selector in use. */ uint64_t select = sextract64(value, 36, 1); - ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx); TLBIRange ret = { }; ARMGranuleSize gran; @@ -11040,11 +11040,11 @@ static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, } ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) + ARMMMUIdx mmu_idx) { uint64_t tcr = regime_tcr(env, mmu_idx); bool epd, hpd, tsz_oob, ds, ha, hd; - int select, tsz, tbi, max_tsz, min_tsz, ps, sh; + int select, tsz, tbii, tbid, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu = env_archcpu(env); bool stage2 = regime_is_stage2(mmu_idx); @@ -11147,18 +11147,18 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, } /* Present TBI as a composite with TBID. */ - tbi = aa64_va_parameter_tbi(tcr, mmu_idx); - if (!data) { - tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi = (tbi >> select) & 1; + tbid = aa64_va_parameter_tbi(tcr, mmu_idx); + tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); + tbid = (tbid >> select) & 1; + tbii = (tbii >> select) & 1; return (ARMVAParameters) { .tsz = tsz, .ps = ps, .sh = sh, .select = select, - .tbi = tbi, + .tbid = tbid, + .tbii = tbii, .epd = epd, .hpd = hpd, .tsz_oob = tsz_oob, diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index d0483bf051..bfed6f9722 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -293,19 +293,20 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx); uint64_t pac, ext_ptr, ext, test; int bot_bit, top_bit; + bool tbi = data ? param.tbid : param.tbii; /* If tagged pointers are in use, use ptr<55>, otherwise ptr<63>. */ - if (param.tbi) { + if (tbi) { ext = sextract64(ptr, 55, 1); } else { ext = sextract64(ptr, 63, 1); } /* Build a pointer with known good extension bits. */ - top_bit = 64 - 8 * param.tbi; + top_bit = 64 - 8 * tbi; bot_bit = 64 - param.tsz; ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext); @@ -328,7 +329,7 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, * Preserve the determination between upper and lower at bit 55, * and insert pointer authentication code. */ - if (param.tbi) { + if (tbi) { ptr &= ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit + 1); pac &= MAKE_64BIT_MASK(bot_bit, 54 - bot_bit + 1); } else { @@ -339,12 +340,12 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, return pac | ext | ptr; } -static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +static uint64_t pauth_original_ptr(uint64_t ptr, int tsz, bool tbi) { /* Note that bit 55 is used whether or not the regime has 2 ranges. */ uint64_t extfield = sextract64(ptr, 55, 1); - int bot_pac_bit = 64 - param.tsz; - int top_pac_bit = 64 - 8 * param.tbi; + int bot_pac_bit = 64 - tsz; + int top_pac_bit = 64 - 8 * tbi; return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); } @@ -353,19 +354,20 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx); + bool tbi = data ? param.tbid : param.tbii; int bot_bit, top_bit; uint64_t pac, orig_ptr, test; - orig_ptr = pauth_original_ptr(ptr, param); + orig_ptr = pauth_original_ptr(ptr, param.tsz, tbi); pac = pauth_computepac(env, orig_ptr, modifier, *key); bot_bit = 64 - param.tsz; - top_bit = 64 - 8 * param.tbi; + top_bit = 64 - 8 * tbi; test = (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1); if (unlikely(extract64(test, bot_bit, top_bit - bot_bit))) { int error_code = (keynumber << 1) | (keynumber ^ 1); - if (param.tbi) { + if (tbi) { return deposit64(orig_ptr, 53, 2, error_code); } else { return deposit64(orig_ptr, 61, 2, error_code); @@ -377,9 +379,10 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx); + bool tbi = data ? param.tbid : param.tbii; - return pauth_original_ptr(ptr, param); + return pauth_original_ptr(ptr, param.tsz, tbi); } static G_NORETURN diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 57f3615a66..a19d714985 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1193,8 +1193,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, if (aarch64) { int ps; - param = aa64_va_parameters(env, address, mmu_idx, - access_type != MMU_INST_FETCH); + param = aa64_va_parameters(env, address, mmu_idx); level = 0; /* @@ -1210,7 +1209,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, goto do_translation_fault; } - addrsize = 64 - 8 * param.tbi; + addrsize = access_type == MMU_INST_FETCH ? param.tbii : param.tbid; + addrsize = 64 - 8 * addrsize; inputsize = 64 - param.tsz; /*