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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id b4-20020a17090a7ac400b0022c35afad5bsm2496763pjl.16.2023.02.01.23.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 23:52:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: anders.roxell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 1/4] target/arm: Flush only required tlbs for TCR_EL[12] Date: Wed, 1 Feb 2023 21:52:39 -1000 Message-Id: <20230202075242.260793-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230202075242.260793-1-richard.henderson@linaro.org> References: <20230202075242.260793-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ASID only affects stage1 of the relevant regime. Signed-off-by: Richard Henderson --- target/arm/helper.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72b37b7cf1..8ad9a667f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4054,13 +4054,30 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } -static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, +static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); - /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ - tlb_flush(CPU(cpu)); + /* For AA64, the A1 or AS bits could result in a change of ASID. */ + tlb_flush_by_mmuidx(cs, (ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0)); + raw_write(env, ri, value); +} + +static void vmsa_tcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs = env_cpu(env); + + /* + * For AA64, the A1 or AS bits could result in a change of ASID. + * This only affects the EL2&0 regime, not the EL2 regime. + */ + tlb_flush_by_mmuidx(cs, (ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0)); raw_write(env, ri, value); } @@ -4151,7 +4168,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .access = PL1_RW, .accessfn = access_tvm_trvm, - .writefn = vmsa_tcr_el12_write, + .writefn = vmsa_tcr_el1_write, .raw_writefn = raw_write, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, @@ -5894,7 +5911,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .resetvalue = 0 }, { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, - .access = PL2_RW, .writefn = vmsa_tcr_el12_write, + .access = PL2_RW, .writefn = vmsa_tcr_el2_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name = "VTCR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,