[PULL,15/27] tcg/s390x: Support MIE2 MGRK instruction

Message ID	20230107075118.1814503-16-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich <iii@linux.ibm.com> Subject: [PULL 15/27] tcg/s390x: Support MIE2 MGRK instruction Date: Fri, 6 Jan 2023 23:51:06 -0800 Message-Id: <20230107075118.1814503-16-richard.henderson@linaro.org> In-Reply-To: <20230107075118.1814503-1-richard.henderson@linaro.org> References: <20230107075118.1814503-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/27] tcg/s390x: Use register pair allocation for div and mulu2 \| expand [PULL,01/27] tcg/s390x: Use register pair allocation for div and mulu2 [PULL,02/27] tcg/s390x: Remove TCG_REG_TB [PULL,03/27] tcg/s390x: Always set TCG_TARGET_HAS_direct_jump [PULL,04/27] tcg/s390x: Remove USE_LONG_BRANCHES [PULL,05/27] tcg/s390x: Check for long-displacement facility at startup [PULL,06/27] tcg/s390x: Check for extended-immediate facility at startup [PULL,07/27] tcg/s390x: Check for general-instruction-extension facility at startup [PULL,08/27] tcg/s390x: Check for load-on-condition facility at startup [PULL,09/27] tcg/s390x: Remove FAST_BCR_SER facility check [PULL,10/27] tcg/s390x: Remove DISTINCT_OPERANDS facility check [PULL,11/27] tcg/s390x: Use LARL+AGHI for odd addresses [PULL,12/27] tcg/s390x: Distinguish RRF-a and RRF-c formats [PULL,13/27] tcg/s390x: Distinguish RIE formats [PULL,14/27] tcg/s390x: Support MIE2 multiply single instructions [PULL,15/27] tcg/s390x: Support MIE2 MGRK instruction [PULL,16/27] tcg/s390x: Issue XILF directly for xor_i32 [PULL,17/27] tcg/s390x: Tighten constraints for or_i64 and xor_i64 [PULL,18/27] tcg/s390x: Tighten constraints for and_i64 [PULL,19/27] tcg/s390x: Support MIE3 logical operations [PULL,20/27] tcg/s390x: Create tgen_cmp2 to simplify movcond [PULL,21/27] tcg/s390x: Generalize movcond implementation [PULL,22/27] tcg/s390x: Support SELGR instruction in movcond [PULL,23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz [PULL,24/27] tcg/s390x: Implement ctpop operation [PULL,25/27] tcg/s390x: Tighten constraints for 64-bit compare [PULL,26/27] tcg/s390x: Cleanup tcg_out_movi [PULL,27/27] tcg/s390x: Avoid the constant pool in tcg_out_movi

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Subject: [PULL 15/27] tcg/s390x: Support MIE2 MGRK instruction
Date: Fri,  6 Jan 2023 23:51:06 -0800
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Series

[PULL,01/27] tcg/s390x: Use register pair allocation for div and mulu2 | expand

Commit Message

Richard Henderson Jan. 7, 2023, 7:51 a.m. UTC

The MIE2 facility adds a 3-operand signed 64x64->128 multiply.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target-con-set.h | 1 +
 tcg/s390x/tcg-target.h         | 2 +-
 tcg/s390x/tcg-target.c.inc     | 8 ++++++++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 33a82e3286..b1a89a88ba 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -31,6 +31,7 @@  C_O1_I3(v, v, v, v)
 C_O1_I4(r, r, ri, r, 0)
 C_O1_I4(r, r, ri, rI, 0)
 C_O2_I2(o, m, 0, r)
+C_O2_I2(o, m, r, r)
 C_O2_I3(o, m, 0, 1, r)
 C_O2_I4(r, r, 0, 1, rA, r)
 C_O2_I4(r, r, 0, 1, ri, r)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 1fb7b8fb1d..03ce11a34a 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -136,7 +136,7 @@  extern uint64_t s390_facilities[3];
 #define TCG_TARGET_HAS_add2_i64       1
 #define TCG_TARGET_HAS_sub2_i64       1
 #define TCG_TARGET_HAS_mulu2_i64      1
-#define TCG_TARGET_HAS_muls2_i64      0
+#define TCG_TARGET_HAS_muls2_i64      HAVE_FACILITY(MISC_INSN_EXT2)
 #define TCG_TARGET_HAS_muluh_i64      0
 #define TCG_TARGET_HAS_mulsh_i64      0
 
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 9634126ed1..871fcb7683 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -175,6 +175,7 @@  typedef enum S390Opcode {
     RRE_SLBGR   = 0xb989,
     RRE_XGR     = 0xb982,
 
+    RRFa_MGRK   = 0xb9ec,
     RRFa_MSRKC  = 0xb9fd,
     RRFa_MSGRKC = 0xb9ed,
     RRFa_NRK    = 0xb9f4,
@@ -2319,6 +2320,11 @@  static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_debug_assert(args[0] == args[1] + 1);
         tcg_out_insn(s, RRE, MLGR, args[1], args[3]);
         break;
+    case INDEX_op_muls2_i64:
+        tcg_debug_assert((args[1] & 1) == 0);
+        tcg_debug_assert(args[0] == args[1] + 1);
+        tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]);
+        break;
 
     case INDEX_op_shl_i64:
         op = RSY_SLLG;
@@ -3009,6 +3015,8 @@  static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
 
     case INDEX_op_mulu2_i64:
         return C_O2_I2(o, m, 0, r);
+    case INDEX_op_muls2_i64:
+        return C_O2_I2(o, m, r, r);
 
     case INDEX_op_add2_i32:
     case INDEX_op_sub2_i32:

[PULL,15/27] tcg/s390x: Support MIE2 MGRK instruction

Commit Message

Patch