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[209.51.188.17]) by mx.google.com with ESMTPS id cn13-20020a05622a248d00b003a82080498csi19559046qtb.754.2023.01.04.14.50.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Jan 2023 14:50:53 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iQ8Bfh7y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pDBva-0002L9-Cf; Wed, 04 Jan 2023 17:08:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBuq-00021x-Tb for qemu-devel@nongnu.org; Wed, 04 Jan 2023 17:07:21 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBun-0005am-JX for qemu-devel@nongnu.org; Wed, 04 Jan 2023 17:07:20 -0500 Received: by mail-ej1-x62f.google.com with SMTP id fc4so85883676ejc.12 for ; Wed, 04 Jan 2023 14:07:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c0SPEwXyflkiw42kdbQzUDTcTHzybkAd3cMquverKqA=; b=iQ8Bfh7ypySwtQudVdpmBFo9jAOECouo6v0Mm2PY8M8ncwvAFnh0Z64MiQzv8j3lfd InWICNpqEmN/un1I+jJEL4aBPj9w/WhIYmJcvSi5Jszhlvl6oINXPlhD6JFWwiT1uawz aDTiXb3hxPztUbUMNZ8MGoUdL3Y2s5jQ8VsOsguUkxqpqe5x64z2jkrYimbuNQee1iuT HiqJueIznICGSdND3aEIK7vgz3jFjolaThFq8Lspo5tcviRDOvTVDaCGgSvL/LaOLFiz 3D2LZliMP+FpUTdTrBgiUO8J5TBHgRnCNTlOkaNcwFWaWY4aH15pg4fIBVsgZ/tgnNRC Th2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c0SPEwXyflkiw42kdbQzUDTcTHzybkAd3cMquverKqA=; b=qndkMUZEkYmYQBH+h1eZ3LlW9AcZCqu5zdgmIy1rEvcjn966V/Tc2BkCRJM+QwOlL0 Wq/EoZ66CKW4VQZ471204Ick/TzjnxV9YUPkvrNchmlna+fV/kCrYDTiiyscZ5EE7lHu SQiSW2I5tfLx0OUo7U+nLLd48Lt0SY3kgqZmn9Z7WSlsXIre2d9JW10Cb1Jr/LlJtJlP lPR3lLgrvbPn1+QpPwSWrEQ0WKy24OBFJvGqtMrkAANBNRksmvlMHdmHDF+JJsttqAte XvpJotj0JMlvtKwuXQCKsroC21+UX2oXwO0WNpu+y5MkybbQaW5gjFW5YBIxH/RFpfNs J8HA== X-Gm-Message-State: AFqh2kqWgoyUhOhfwC0zyrjT79V1FHmwzxwBap5Pbr+fKK2hp6uGIgFR y2G2USVu1kTbXaTqOU1CfMlDAzFr5AKu2V3m X-Received: by 2002:a17:907:86a6:b0:7c0:fd1a:79f0 with SMTP id qa38-20020a17090786a600b007c0fd1a79f0mr59298049ejc.21.1672870030224; Wed, 04 Jan 2023 14:07:10 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id h14-20020a1709063c0e00b00780b1979adesm15773759ejg.218.2023.01.04.14.07.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:07:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 16/20] hw/block: Factor pflash_cfi02_create() out of pflash_cfi02_register() Date: Wed, 4 Jan 2023 23:04:45 +0100 Message-Id: <20230104220449.41337-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Currently pflash_cfi02_register(): 1/ creates a TYPE_PFLASH_CFI02 qdev instance 2/ maps the first MMIO region to the system bus The first minor issue is the implicit sysbus mapping is not obvious (the function name could mention it), and the function is not documented. Another issue is we are forced to map on sysbus, thus code wanting to simply instantiate this device are forced to open code the qdev creation. This is a problem in a heterogeneous system where not all cores has access to the sysbus, or if we want to map the pflash on different address spaces. To clarify this API, extract the qdev creation in a new helper named pflash_cfi02_create(). We don't document pflash_cfi02_register() because we are going to remove it in a pair of commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/block/pflash_cfi02.c | 55 ++++++++++++++++++++++++++-------------- include/hw/block/flash.h | 14 +++++++++- 2 files changed, 49 insertions(+), 20 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 2a99b286b0..176f93b512 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -994,6 +994,37 @@ static void pflash_cfi02_register_types(void) type_init(pflash_cfi02_register_types) +DeviceState *pflash_cfi02_create(const char *name, hwaddr size, + BlockBackend *blk, uint32_t sector_len, + int nb_mappings, int bank_width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + uint16_t unlock_addr0, uint16_t unlock_addr1, + int be) +{ + DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02); + + if (blk) { + qdev_prop_set_drive(dev, "drive", blk); + } + assert(QEMU_IS_ALIGNED(size, sector_len)); + qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); + qdev_prop_set_uint32(dev, "sector-length", sector_len); + qdev_prop_set_uint8(dev, "width", bank_width); + qdev_prop_set_uint8(dev, "mappings", nb_mappings); + qdev_prop_set_uint8(dev, "big-endian", !!be); + qdev_prop_set_uint16(dev, "id0", id0); + qdev_prop_set_uint16(dev, "id1", id1); + qdev_prop_set_uint16(dev, "id2", id2); + qdev_prop_set_uint16(dev, "id3", id3); + qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); + qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); + qdev_prop_set_string(dev, "name", name); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + return dev; +} + PFlashCFI02 *pflash_cfi02_register(hwaddr base, const char *name, hwaddr size, @@ -1006,26 +1037,12 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, uint16_t unlock_addr1, int be) { - DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02); - - if (blk) { - qdev_prop_set_drive(dev, "drive", blk); - } - assert(QEMU_IS_ALIGNED(size, sector_len)); - qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); - qdev_prop_set_uint32(dev, "sector-length", sector_len); - qdev_prop_set_uint8(dev, "width", width); - qdev_prop_set_uint8(dev, "mappings", nb_mappings); - qdev_prop_set_uint8(dev, "big-endian", !!be); - qdev_prop_set_uint16(dev, "id0", id0); - qdev_prop_set_uint16(dev, "id1", id1); - qdev_prop_set_uint16(dev, "id2", id2); - qdev_prop_set_uint16(dev, "id3", id3); - qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); - qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); - qdev_prop_set_string(dev, "name", name); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + DeviceState *dev; + dev = pflash_cfi02_create(name, size, blk, sector_len, + nb_mappings, width, id0, id1, id2, id3, + unlock_addr0, unlock_addr1, be); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + return PFLASH_CFI02(dev); } diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 321aede8ef..78b078955e 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -32,7 +32,19 @@ void pflash_cfi01_legacy_drive(DeviceState *dev, DriveInfo *dinfo); #define TYPE_PFLASH_CFI02 "cfi.pflash02" OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02) - +/** + * Create and realize a parallel NOR flash (CFI type 2) on the heap. + * + * Create the device state structure, initialize it, and drop the + * reference to it (the device is realized). + */ +DeviceState *pflash_cfi02_create(const char *name, hwaddr size, + BlockBackend *blk, uint32_t sector_len, + int nb_mappings, int bank_width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + uint16_t unlock_addr0, uint16_t unlock_addr1, + int be); PFlashCFI02 *pflash_cfi02_register(hwaddr base, const char *name, hwaddr size,