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([2607:fb90:8060:51a2:184b:6e49:c396:be2]) by smtp.gmail.com with ESMTPSA id v2-20020a05620a440200b006fed2788751sm23042354qkp.76.2023.01.03.10.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:17:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org Subject: [RFC PATCH 07/40] target/arm: Create TYPE_ARM_V7M_CPU Date: Tue, 3 Jan 2023 10:16:13 -0800 Message-Id: <20230103181646.55711-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103181646.55711-1-richard.henderson@linaro.org> References: <20230103181646.55711-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::e2f; envelope-from=richard.henderson@linaro.org; helo=mail-vs1-xe2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create a new intermediate abstract class for v7m, like we do for aarch64. The initialization of ARMCPUClass.info follows the concrete class, so remove that init from arm_v7m_class_init. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu-qom.h | 6 ++++++ target/arm/cpu_tcg.c | 36 ++++++++++++++++++++++-------------- 2 files changed, 28 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 184b3e3726..ae31289582 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -26,6 +26,7 @@ struct arm_boot_info; #define TYPE_ARM_CPU "arm-cpu" +#define TYPE_ARM_V7M_CPU "arm-v7m-cpu" #define TYPE_AARCH64_CPU "aarch64-cpu" OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) @@ -45,6 +46,11 @@ static inline void arm_cpu_register(const ARMCPUInfo *info) arm_cpu_register_parent(info, TYPE_ARM_CPU); } +static inline void arm_v7m_cpu_register(const ARMCPUInfo *info) +{ + arm_cpu_register_parent(info, TYPE_ARM_V7M_CPU); +} + static inline void aarch64_cpu_register(const ARMCPUInfo *info) { arm_cpu_register_parent(info, TYPE_AARCH64_CPU); diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 568cbcfc52..d566a815d3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1056,10 +1056,8 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = { static void arm_v7m_class_init(ObjectClass *oc, void *data) { - ARMCPUClass *acc = ARM_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); - acc->info = data; #ifdef CONFIG_TCG cc->tcg_ops = &arm_v7m_tcg_ops; #endif /* CONFIG_TCG */ @@ -1149,18 +1147,6 @@ static const ARMCPUInfo arm_tcg_cpus[] = { { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn }, - { .name = "cortex-m0", .initfn = cortex_m0_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m3", .initfn = cortex_m3_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m4", .initfn = cortex_m4_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m7", .initfn = cortex_m7_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m33", .initfn = cortex_m33_initfn, - .class_init = arm_v7m_class_init }, - { .name = "cortex-m55", .initfn = cortex_m55_initfn, - .class_init = arm_v7m_class_init }, { .name = "cortex-r5", .initfn = cortex_r5_initfn }, { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, { .name = "ti925t", .initfn = ti925t_initfn }, @@ -1187,6 +1173,24 @@ static const ARMCPUInfo arm_tcg_cpus[] = { #endif }; +static const ARMCPUInfo arm_v7m_tcg_cpus[] = { + { .name = "cortex-m0", .initfn = cortex_m0_initfn }, + { .name = "cortex-m3", .initfn = cortex_m3_initfn }, + { .name = "cortex-m4", .initfn = cortex_m4_initfn }, + { .name = "cortex-m7", .initfn = cortex_m7_initfn }, + { .name = "cortex-m33", .initfn = cortex_m33_initfn }, + { .name = "cortex-m55", .initfn = cortex_m55_initfn }, +}; + +static const TypeInfo arm_v7m_cpu_type_info = { + .name = TYPE_ARM_V7M_CPU, + .parent = TYPE_ARM_CPU, + .instance_size = sizeof(ARMCPU), + .abstract = true, + .class_size = sizeof(ARMCPUClass), + .class_init = arm_v7m_class_init, +}; + static const TypeInfo idau_interface_type_info = { .name = TYPE_IDAU_INTERFACE, .parent = TYPE_INTERFACE, @@ -1197,10 +1201,14 @@ static void arm_tcg_cpu_register_types(void) { size_t i; + type_register_static(&arm_v7m_cpu_type_info); type_register_static(&idau_interface_type_info); for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } + for (i = 0; i < ARRAY_SIZE(arm_v7m_tcg_cpus); ++i) { + arm_v7m_cpu_register(&arm_v7m_tcg_cpus[i]); + } } type_init(arm_tcg_cpu_register_types)