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([2607:fb90:8060:51a2:184b:6e49:c396:be2]) by smtp.gmail.com with ESMTPSA id v2-20020a05620a440200b006fed2788751sm23042354qkp.76.2023.01.03.10.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:18:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org Subject: [RFC PATCH 34/40] target/arm: Move "reset-hivecs" to class property Date: Tue, 3 Jan 2023 10:16:40 -0800 Message-Id: <20230103181646.55711-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103181646.55711-1-richard.henderson@linaro.org> References: <20230103181646.55711-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::e30; envelope-from=richard.henderson@linaro.org; helo=mail-vs1-xe30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove the reset_hivecs variable entirely and create property accessor functions that directly read/write a bit of the reset value of SCTLR. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 - hw/arm/digic.c | 11 ++++----- hw/arm/npcm7xx.c | 9 ++++---- hw/arm/xlnx-zynqmp.c | 11 +++++---- target/arm/cpu.c | 55 +++++++++++++++++++++++++++++++++----------- 5 files changed, 59 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e425846007..c0baec37d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -973,7 +973,6 @@ struct ArchCPU { uint64_t ccsidr[16]; uint64_t reset_cbar; uint32_t reset_auxcr; - bool reset_hivecs; /* * Intermediate values used during property parsing. diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 6df5547977..fed5d38695 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -34,9 +34,13 @@ static void digic_init(Object *obj) { DigicState *s = DIGIC(obj); + const char *cpu_type = ARM_CPU_TYPE_NAME("arm946"); + ObjectClass *cpu_class = object_class_by_name(cpu_type); int i; - object_initialize_child(obj, "cpu", &s->cpu, ARM_CPU_TYPE_NAME("arm946")); + class_property_set_bool(cpu_class, "reset-hivecs", true, &error_abort); + + object_initialize_child(obj, "cpu", &s->cpu, cpu_type); for (i = 0; i < DIGIC4_NB_TIMERS; i++) { g_autofree char *name = g_strdup_printf("timer[%d]", i); @@ -52,11 +56,6 @@ static void digic_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd; int i; - if (!object_property_set_bool(OBJECT(&s->cpu), "reset-hivecs", true, - errp)) { - return; - } - if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { return; } diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 41124b7444..97ac4ac7e9 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -390,11 +390,14 @@ static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) static void npcm7xx_init(Object *obj) { NPCM7xxState *s = NPCM7XX(obj); + const char *cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); + ObjectClass *cpu_class = object_class_by_name(cpu_type); int i; + class_property_set_bool(cpu_class, "reset-hivecs", true, &error_abort); + for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { - object_initialize_child(obj, "cpu[*]", &s->cpu[i], - ARM_CPU_TYPE_NAME("cortex-a9")); + object_initialize_child(obj, "cpu[*]", &s->cpu[i], cpu_type); } object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); @@ -466,8 +469,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); - object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, - &error_abort); /* Disable security extensions. */ object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 335cfc417d..13ab999eb8 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -243,8 +243,6 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, s->boot_cpu_ptr = &s->rpu_cpu[i]; } - object_property_set_bool(OBJECT(&s->rpu_cpu[i]), "reset-hivecs", true, - &error_abort); if (!qdev_realize(DEVICE(&s->rpu_cpu[i]), NULL, errp)) { return; } @@ -375,6 +373,8 @@ static void xlnx_zynqmp_init(Object *obj) { MachineState *ms = MACHINE(qdev_get_machine()); XlnxZynqMPState *s = XLNX_ZYNQMP(obj); + const char *cpu_type; + ObjectClass *cpu_class; int i; int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); @@ -382,10 +382,13 @@ static void xlnx_zynqmp_init(Object *obj) TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); + cpu_class = object_class_by_name(cpu_type); + class_property_set_bool(cpu_class, "reset-hivecs", true, &error_abort); + for (i = 0; i < num_apus; i++) { object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", - &s->apu_cpu[i], - ARM_CPU_TYPE_NAME("cortex-a53")); + &s->apu_cpu[i], cpu_type); } object_initialize_child(obj, "gic", &s->gic, gic_class_name()); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bc4a052e4c..032a2cc00a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1280,9 +1280,6 @@ static void arm_cpu_initfn(Object *obj) static Property arm_cpu_reset_cbar_property = DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); -static Property arm_cpu_reset_hivecs_property = - DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); - #ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property = DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); @@ -1375,10 +1372,6 @@ static void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); } - if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); - } - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, @@ -1801,10 +1794,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } - if (cpu->reset_hivecs) { - cpu->reset_sctlr |= (1 << 13); - } - if (cpu->cfgend) { if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { cpu->reset_sctlr |= SCTLR_EE; @@ -2169,6 +2158,39 @@ static bool arm_class_prop_uint64_ofs(ObjectClass *oc, Visitor *v, return visit_type_uint64(v, name, ptr, errp); } +#ifndef CONFIG_USER_ONLY +static bool arm_class_prop_set_sctlrbit(ObjectClass *oc, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARMCPUClass *acc = ARM_CPU_CLASS(oc); + uint32_t mask = (uintptr_t)opaque; + bool val; + + if (!visit_type_bool(v, name, &val, errp)) { + return false; + } + + if (val) { + acc->reset_sctlr |= mask; + } else { + acc->reset_sctlr &= ~mask; + } + return true; +} + +static bool arm_class_prop_get_sctlrbit(ObjectClass *oc, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARMCPUClass *acc = ARM_CPU_CLASS(oc); + uint32_t mask = (uintptr_t)opaque; + bool val = acc->reset_sctlr & mask; + + return visit_type_bool(v, name, &val, errp); +} +#endif /* !CONFIG_USER_ONLY */ + static void arm_cpu_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc = ARM_CPU_CLASS(oc); @@ -2305,7 +2327,14 @@ static void arm_cpu_leaf_class_init(ObjectClass *oc, void *data) (void *)(uintptr_t) offsetof(ARMCPUClass, gt_cntfrq_hz)); } -#endif /* CONFIG_USER_ONLY */ + + if (!arm_class_feature(acc, ARM_FEATURE_M)) { + class_property_add(oc, "reset-hivecs", "bool", NULL, + arm_class_prop_get_sctlrbit, + arm_class_prop_set_sctlrbit, + (void *)((uintptr_t)1 << 13)); + } +#endif /* !CONFIG_USER_ONLY */ } static bool arm_cpu_class_late_init(ObjectClass *oc, Error **errp) @@ -2324,7 +2353,7 @@ static bool arm_cpu_class_late_init(ObjectClass *oc, Error **errp) error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", acc->gt_cntfrq_hz); return false; } -#endif /* CONFIG_USER_ONLY */ +#endif /* !CONFIG_USER_ONLY */ /* Run some consistency checks for TCG. */ if (tcg_enabled()) {