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([2607:fb90:8060:51a2:184b:6e49:c396:be2]) by smtp.gmail.com with ESMTPSA id v2-20020a05620a440200b006fed2788751sm23042354qkp.76.2023.01.03.10.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:18:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org Subject: [RFC PATCH 25/40] target/arm/hvf: Use offsetof in hvf_arm_get_host_cpu_features Date: Tue, 3 Jan 2023 10:16:31 -0800 Message-Id: <20230103181646.55711-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103181646.55711-1-richard.henderson@linaro.org> References: <20230103181646.55711-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::e36; envelope-from=richard.henderson@linaro.org; helo=mail-vs1-xe36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use an offsetof vs ARMCPUClass, which means that the regs[] array may be static const, and we can include midr in the list. Signed-off-by: Richard Henderson --- target/arm/hvf/hvf.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index d47159b9bf..362dd4ac2e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -459,19 +459,29 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) bool hvf_arm_get_host_cpu_features(ARMCPUClass *acc, Error **errp) { - const struct isar_regs { - int reg; - uint64_t *val; + static const struct isar_regs { + int reg, offset; } regs[] = { - { HV_SYS_REG_ID_AA64PFR0_EL1, &acc->isar.id_aa64pfr0 }, - { HV_SYS_REG_ID_AA64PFR1_EL1, &acc->isar.id_aa64pfr1 }, - { HV_SYS_REG_ID_AA64DFR0_EL1, &acc->isar.id_aa64dfr0 }, - { HV_SYS_REG_ID_AA64DFR1_EL1, &acc->isar.id_aa64dfr1 }, - { HV_SYS_REG_ID_AA64ISAR0_EL1, &acc->isar.id_aa64isar0 }, - { HV_SYS_REG_ID_AA64ISAR1_EL1, &acc->isar.id_aa64isar1 }, - { HV_SYS_REG_ID_AA64MMFR0_EL1, &acc->isar.id_aa64mmfr0 }, - { HV_SYS_REG_ID_AA64MMFR1_EL1, &acc->isar.id_aa64mmfr1 }, - { HV_SYS_REG_ID_AA64MMFR2_EL1, &acc->isar.id_aa64mmfr2 }, + { HV_SYS_REG_ID_AA64PFR0_EL1, + offsetof(ARMCPUClass, isar.id_aa64pfr0) }, + { HV_SYS_REG_ID_AA64PFR1_EL1, + offsetof(ARMCPUClass, isar.id_aa64pfr1) }, + { HV_SYS_REG_ID_AA64DFR0_EL1, + offsetof(ARMCPUClass, isar.id_aa64dfr0) }, + { HV_SYS_REG_ID_AA64DFR1_EL1, + offsetof(ARMCPUClass, isar.id_aa64dfr1) }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, + offsetof(ARMCPUClass, isar.id_aa64isar0) }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, + offsetof(ARMCPUClass, isar.id_aa64isar1) }, + { HV_SYS_REG_ID_AA64MMFR0_EL1, + offsetof(ARMCPUClass, isar.id_aa64mmfr0) }, + { HV_SYS_REG_ID_AA64MMFR1_EL1, + offsetof(ARMCPUClass, isar.id_aa64mmfr1) }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, + offsetof(ARMCPUClass, isar.id_aa64mmfr2) }, + { HV_SYS_REG_MIDR_EL1, + offsetof(ARMCPUClass, midr) }, }; hv_vcpu_t fd; hv_return_t r = HV_SUCCESS; @@ -485,9 +495,9 @@ bool hvf_arm_get_host_cpu_features(ARMCPUClass *acc, Error **errp) } for (i = 0; i < ARRAY_SIZE(regs); i++) { - r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val); + uint64_t *p = (void *)acc + regs[i].offset; + r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, p); } - r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &acc->midr); r |= hv_vcpu_destroy(fd); /*