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([2607:fb90:8060:51a2:184b:6e49:c396:be2]) by smtp.gmail.com with ESMTPSA id v2-20020a05620a440200b006fed2788751sm23042354qkp.76.2023.01.03.10.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:17:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, berrange@redhat.com, eduardo@habkost.net, armbru@redhat.com, ajones@ventanamicro.com, alex.bennee@linaro.org Subject: [RFC PATCH 10/40] target/arm: Copy dtb_compatible from ARMCPUClass Date: Tue, 3 Jan 2023 10:16:16 -0800 Message-Id: <20230103181646.55711-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103181646.55711-1-richard.henderson@linaro.org> References: <20230103181646.55711-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::e2f; envelope-from=richard.henderson@linaro.org; helo=mail-vs1-xe2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move the default initialization of dtb_compatible to arm_cpu_class_init, and copy back to the instance in arm_cpu_init. Further class overrides will come in a future patch. Signed-off-by: Richard Henderson --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu.c | 15 ++++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 057978b9db..5509ef9d85 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -71,6 +71,9 @@ struct ARMCPUClass { const ARMCPUInfo *info; DeviceRealize parent_realize; ResettablePhases parent_phases; + + /* 'compatible' string for this CPU for Linux device trees */ + const char *dtb_compatible; }; void register_cp_regs_for_features(ARMCPU *cpu); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a6c6916f36..1bc45b2b25 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1181,6 +1181,7 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); cpu_set_cpustate_pointers(cpu); cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, @@ -1189,6 +1190,8 @@ static void arm_cpu_initfn(Object *obj) QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); + cpu->dtb_compatible = acc->dtb_compatible; + #ifdef CONFIG_USER_ONLY # ifdef TARGET_AARCH64 /* @@ -1220,11 +1223,6 @@ static void arm_cpu_initfn(Object *obj) "pmu-interrupt", 1); #endif - /* DTB consumers generally don't in fact care what the 'compatible' - * string is, so always provide some string and trust that a hypothetical - * picky DTB consumer will also provide a helpful error message. - */ - cpu->dtb_compatible = "qemu,unknown"; cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; @@ -2243,6 +2241,13 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #ifdef CONFIG_TCG cc->tcg_ops = &arm_tcg_ops; #endif /* CONFIG_TCG */ + + /* + * DTB consumers generally don't in fact care what the 'compatible' + * string is, so always provide some string and trust that a hypothetical + * picky DTB consumer will also provide a helpful error message. + */ + acc->dtb_compatible = "qemu,unknown"; } static void arm_cpu_leaf_class_init(ObjectClass *oc, void *data)