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Iglesias" , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 6/6] hw/arm/boot: Remove tswap32() calls and constify board_setup_blob[] Date: Thu, 22 Dec 2022 22:55:49 +0100 Message-Id: <20221222215549.86872-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM CPUs fetch instructions in little-endian. board_setup_blob[] encoded instructions are written in little-endian. We call tswap32() on the array. tswap32 function swap a 32-bit value if the target endianness doesn't match the host one. Otherwise it is a NOP. * On a little-endian host, the array is stored as it. tswap32() is a NOP, and the vCPU fetches the instructions as it, in little-endian. * On a big-endian host, the array is stored as it. tswap32() swap the instructions to little-endian, and the vCPU fetches the instructions as it, in little-endian. Using tswap() on system emulation is a bit odd: while the target particularities might change the system emulation, the host ones (such its endianness) shouldn't interfere. We can simplify by using const_le32() to always store the instructions in the array in little-endian, removing the need for the dubious tswap(). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/boot.c | 52 ++++++++++++++++++++++----------------------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3d7d11f782..22a100f19b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -189,7 +189,7 @@ static void write_bootloader(const char *name, hwaddr addr, default: abort(); } - code[i] = tswap32(insn); + code[i] = cpu_to_le32(insn); } assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); @@ -222,34 +222,33 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, hwaddr mvbar_addr) { AddressSpace *as = arm_boot_address_space(cpu, info); - int n; - uint32_t mvbar_blob[] = { + static const uint32_t mvbar_blob[] = { /* mvbar_addr: secure monitor vectors * Default unimplemented and unused vectors to spin. Makes it * easier to debug (as opposed to the CPU running away). */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xe1b0f00e), /* movs pc, lr ;SMC exception return */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe) /* (spin) */ }; - uint32_t board_setup_blob[] = { + const uint32_t board_setup_blob[] = { /* board setup addr */ - 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ - 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ - 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ - 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ - 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ - 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ - 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ - 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ - 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ - 0xe1600070, /* smc #0 ;call monitor to flush SCR */ - 0xe1a0f001, /* mov pc, r1 ;return */ + const_le32(0xee110f51), /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ + const_le32(0xe3800b03), /* orr r0, #0xc00 ;set CP11, CP10 */ + const_le32(0xee010f51), /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ + const_le32(0xe3a00e00 + (mvbar_addr >> 4)), /* mov r0, #mvbar_addr */ + const_le32(0xee0c0f30), /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ + const_le32(0xee110f11), /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ + const_le32(0xe3800031), /* orr r0, #0x31 ;enable AW, FW, NS */ + const_le32(0xee010f11), /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ + const_le32(0xe1a0100e), /* mov r1, lr ;save LR across SMC */ + const_le32(0xe1600070), /* smc #0 ;call monitor to flush SCR */ + const_le32(0xe1a0f001) /* mov pc, r1 ;return */ }; /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ @@ -259,15 +258,8 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); - for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { - mvbar_blob[n] = tswap32(mvbar_blob[n]); - } rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), mvbar_addr, as); - - for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { - board_setup_blob[n] = tswap32(board_setup_blob[n]); - } rom_add_blob_fixed_as("board-setup", board_setup_blob, sizeof(board_setup_blob), info->board_setup_addr, as); }