From patchwork Wed Dec 21 22:39:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 635642 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3778872pvb; Wed, 21 Dec 2022 14:41:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXuCMqaZS+/TjObkT7JsktB9ZwKjEifMvappDU7nOeh+NpkXwan5iEq+5J6LVj/SeosSW3cm X-Received: by 2002:ad4:5589:0:b0:4c7:9e7d:83d8 with SMTP id f9-20020ad45589000000b004c79e7d83d8mr20403682qvx.1.1671662516993; Wed, 21 Dec 2022 14:41:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671662516; cv=none; d=google.com; s=arc-20160816; b=08MHrsoWV+mKV1ZgIBl42cItqvJVHazeBYW+vPpPHoaCmJmgMe9AEPf0loOTHKg+3/ HMb29+XgUijc00HYdfFJ/KcJzveKmBQTw2idz0Dd9sSSixDz+2BWIOgiSlR6zK6yc3J1 ivx+XAUBKHqLhI/wLapK6KQYqNJ59Huzwxf0Cz2wTgMmuUwbjC4MrBuGq0Ok5fFg//3p uZbNDTox9TCgqGeY+IkdC3RUOwIoOC3M5ZB6HSgFFVs4xXCQLKiux4T5W9ezeZXPJnGJ 7aB3p4pWNWwaExcd+w6sLdUU629wKAQFec5/iNxjjTHl8IeDxMfWjvMUxVmpkWDyftdH w+tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=D5RY5Kk/nceV1oQAkjPdC/yhgl/phDrK6jPMk3pLOYI=; b=VpDIMCJs2L5lBKpVxyB4Njv34qPIuHNMLj6MDH5b+D0zbknu+Doq8bijgCVZzkSGik h+2BIPSTL8252U+l0WqIpQm2iw0DbCRV5Xb5YF9ao9f1U5WVqGzWLPpYM8NOkzzc0f9U SE1rVPcKE2PyTXwsv0s/m67BYOcypZFZVhnP4V3JlcxPjfss12nfRORumliT4crpIenZ auoao2nBlfAP5xoO9eulLWZP0YaZ2ALEq3W9AWjl59jWPgTjKyWQVtQpdEv+DvDDbLtr ZKbP31XXOur1BdahkI01Sw9y3G5SJ1uOZL+TgKqJFp15IZwZXSnHfNHQnO0ozbuRy+C5 d/0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=F8EXDoUf; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b="TqcX/z1w"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q2-20020ad45ca2000000b004c68b87e5a0si6862591qvh.366.2022.12.21.14.41.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Dec 2022 14:41:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=F8EXDoUf; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b="TqcX/z1w"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p87lk-0007OM-QW; Wed, 21 Dec 2022 17:41:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p87lj-0007Nl-2T for qemu-devel@nongnu.org; Wed, 21 Dec 2022 17:40:59 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p87lc-0000Xf-1W for qemu-devel@nongnu.org; Wed, 21 Dec 2022 17:40:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1671662451; x=1703198451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wLon510VHyvWrBnIFxTDZasif/XairXPaP+olplQ0og=; b=F8EXDoUffAEBrwmSnkq36QwEOjxilHV4YFj7HdCzl9cnzPZbb+6iNqfx ybcWPea9ApCOM6Z5Z6W8uJH98Ni2JC81/VuytTJsh9dQPuMvv+fcF6Uxn 5xw2VVHzvJ+ii3pxz50Yss13if/8gqDTaQgp72jjftPAtM53zMfE6l0/k EmvWRTX3hmLpGqapMwD30LuFd47aSAg7IZpZNDeMsPUQ7EWH8PSDRSGId 34hCYJy/LdL2J8nUXDVmUP3aVO2OmgAKddVeNbl16cXrC1+S7f5VhGv7W ijobtgKDzH1CiOnN0yRklvZeV5fWoeOQGFWo2V4Yod1ezKlHsx0DD//2M w==; X-IronPort-AV: E=Sophos;i="5.96,263,1665417600"; d="scan'208";a="323561283" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 22 Dec 2022 06:40:41 +0800 IronPort-SDR: jo66Iu3gIRbvwbIrQMB5p1dn4VaTwxSup9YUcxrwyONx7Me+7J+K4gBTSUKGzyDMfLuMg+QGM3 XBf6a7f8YOU3xXzBVhjyd/Z9CtccbOfNYpgN+kMtdEHpUkYyOXRX34fdxkDSUWgc045JYiMydh vpf8YHaCBACB6G3mXmJ5Sj5czM4G1XsqAtMqv4Kcdguyo2SgfWuKTsqFn9mcxXnmINMCaHO7vq 6Sf+i83y1WmAAZl86c35cXsjXHWT9T0hvjoAuJLWSM3etAbsILObeD0os8cPGMLgVNSGI+2C9w aog= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Dec 2022 13:53:10 -0800 IronPort-SDR: wGb2i3jAk1HcJiVNPn9J50lRT/JwzLPJQN5QE7HzWiIUlk0vUWCQn19dpz/CI4qZrnBZpG3lMu 3NyWvhHxbSrM4MYPCXbJvvCLXiecX1lddGdG1TNffhU1SFYieCGSxG6XgeNm0juWuCu47/yiM1 Z3dUs+OcM6fCJv/44k7RDuXNkGRfGA4gYxbhoJTpgCP8tKNjA3notdEuUxwUNHDCAD3w4avMV9 6KPUHNQv061PAGw6XSBRNoIW4L4j2O2Kurl8dD2Hubx6nqUoK5E5YRTD0rYhOfv/RQbA2jL9vc R38= WDCIronportException: Internal Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Dec 2022 14:40:42 -0800 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4NcpLd5F0nz1Rwt8 for ; Wed, 21 Dec 2022 14:40:41 -0800 (PST) Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1671662441; x=1674254442; bh=wLon510VHyvWrBnIFx TDZasif/XairXPaP+olplQ0og=; b=TqcX/z1wwwRPinwpR4Gh0up30R23mCQHPF +N1aNyJKqXkHMiG/zF6yk19gtSz1flUscb5oBn9qtNrQOtks1ina3d/CL6EblKzo IOriRmw1d/7wxS/nDiHOtvWYOQqw2Hk4wx3+PJs65zV0Zggl/WN7D5hWeuY6SBcz 7PxNXwMI8a4VnaE2ATV+nUGrUhD7cIfcQlzNk9kHjMJ8lyiRh0IIUKmjj7fYB609 nhmad5r+SkMegUI5NCryMsa+7HZdywZxwrqhyOfIaENJC+cUkddqApl2JigxRFf2 OuDA6Gqm/kuz9M1Rn+BXoi+n20U6zOuYox6EAhWp2N5sGUNLR1Dg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id HNsGv5D0rwSx for ; Wed, 21 Dec 2022 14:40:41 -0800 (PST) Received: from toolbox.alistair23.me (unknown [10.225.167.8]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4NcpLb3MF3z1Rwrq; Wed, 21 Dec 2022 14:40:39 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Date: Thu, 22 Dec 2022 08:39:43 +1000 Message-Id: <20221221224022.425831-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> References: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=3472792e2=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set base after each step of the address arithmetic instead of before. Return the base register used from tcg_out_tlb_load, so as to keep that register choice localized to that function. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 39 +++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2a84c57bec..e3b608034f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -923,9 +923,9 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) tcg_debug_assert(ok); } -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, + TCGReg addrh, MemOpIdx oi, + tcg_insn_unit **label_ptr, bool is_load) { MemOp opc = get_memop(oi); unsigned s_bits = opc & MO_SIZE; @@ -975,6 +975,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, addrl = TCG_REG_TMP0; } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); + return TCG_REG_TMP0; } static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, @@ -1177,7 +1178,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base = TCG_REG_TMP0; + TCGReg base; data_regl = *args++; data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); @@ -1187,23 +1188,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } a_bits = get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, a_bits); } + base = addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base = TCG_REG_TMP0; + } if (guest_base != 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); + base = TCG_REG_TMP0; } tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); #endif @@ -1249,7 +1252,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base = TCG_REG_TMP0; + TCGReg base; data_regl = *args++; data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); @@ -1259,23 +1262,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } a_bits = get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_regl, a_bits); } + base = addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base = TCG_REG_TMP0; + } if (guest_base != 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); + base = TCG_REG_TMP0; } tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); #endif