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Sat, 17 Dec 2022 09:30:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Max Filippov , Richard Henderson , Bin Meng , kvm@vger.kernel.org, qemu-ppc@nongnu.org, Greg Kurz , Daniel Henrique Barboza , Bernhard Beschow , qemu-riscv@nongnu.org, Song Gao , Artyom Tarasenko , Paolo Bonzini , Palmer Dabbelt , Mark Cave-Ayland , Laurent Vivier , Alistair Francis , =?utf-8?q?C=C3=A9dric_Le_Goate?= =?utf-8?q?r?= , David Gibson , Xiaojuan Yang , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 6/9] target/riscv/cpu: Move Floating-Point fields closer Date: Sat, 17 Dec 2022 18:29:04 +0100 Message-Id: <20221217172907.8364-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221217172907.8364-1-philmd@linaro.org> References: <20221217172907.8364-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fc1f72e5c3..05fafebff7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -143,7 +143,6 @@ typedef struct PMUCTRState { struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ - uint64_t fpr[32]; /* assume both F and D extensions */ /* vector coprocessor state. */ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); @@ -158,7 +157,10 @@ struct CPUArchState { target_ulong load_res; target_ulong load_val; + /* Floating-Point state */ + uint64_t fpr[32]; /* assume both F and D extensions */ target_ulong frm; + float_status fp_status; target_ulong badaddr; target_ulong bins; @@ -372,8 +374,6 @@ struct CPUArchState { target_ulong cur_pmmask; target_ulong cur_pmbase; - float_status fp_status; - /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */