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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id u17-20020a05600c19d100b003c6f8d30e40sm9728258wmq.31.2022.11.25.03.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:52:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , "Michael S. Tsirkin" , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Greg Kurz , Marcel Apfelbaum , qemu-ppc@nongnu.org Subject: [PATCH for-8.0 1/7] hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset Date: Fri, 25 Nov 2022 11:52:34 +0000 Message-Id: <20221125115240.3005559-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221125115240.3005559-1-peter.maydell@linaro.org> References: <20221125115240.3005559-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the TYPE_VIRTIO_PCI class to 3-phase reset. This is necessary so that we can convert the subclass TYPE_VIRTIO_VGA_BASE also to 3-phase reset. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a1c9dfa7bb5..7873083b860 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2008,9 +2008,10 @@ static void virtio_pci_reset(DeviceState *qdev) } } -static void virtio_pci_bus_reset(DeviceState *qdev) +static void virtio_pci_bus_reset_hold(Object *obj) { - PCIDevice *dev = PCI_DEVICE(qdev); + PCIDevice *dev = PCI_DEVICE(obj); + DeviceState *qdev = DEVICE(obj); virtio_pci_reset(qdev); @@ -2071,6 +2072,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); VirtioPCIClass *vpciklass = VIRTIO_PCI_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); device_class_set_props(dc, virtio_pci_properties); k->realize = virtio_pci_realize; @@ -2080,7 +2082,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_OTHERS; device_class_set_parent_realize(dc, virtio_pci_dc_realize, &vpciklass->parent_dc_realize); - dc->reset = virtio_pci_bus_reset; + rc->phases.hold = virtio_pci_bus_reset_hold; } static const TypeInfo virtio_pci_info = {