| Message ID | 20221124115023.2437291-6-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Convert most CPU classes to 3-phase reset | expand |
> -----Original Message----- > From: Peter Maydell <peter.maydell@linaro.org> > Sent: Thursday, November 24, 2022 5:50 AM > To: qemu-devel@nongnu.org > Cc: Peter Maydell <peter.maydell@linaro.org>; Michael Rolnik > <mrolnik@gmail.com>; Edgar E. Iglesias <edgar.iglesias@gmail.com>; Taylor > Simpson <tsimpson@quicinc.com>; Song Gao <gaosong@loongson.cn>; > Xiaojuan Yang <yangxiaojuan@loongson.cn>; Laurent Vivier > <laurent@vivier.eu>; Philippe Mathieu-Daudé <philmd@linaro.org>; > Aurelien Jarno <aurelien@aurel32.net>; Jiaxun Yang > <jiaxun.yang@flygoat.com>; Aleksandar Rikalo > <aleksandar.rikalo@syrmia.com>; Chris Wulff <crwulff@gmail.com>; Marek > Vasut <marex@denx.de>; Stafford Horne <shorne@gmail.com>; Daniel > Henrique Barboza <danielhb413@gmail.com>; Cédric Le Goater > <clg@kaod.org>; David Gibson <david@gibson.dropbear.id.au>; Greg Kurz > <groug@kaod.org>; Palmer Dabbelt <palmer@dabbelt.com>; Alistair Francis > <alistair.francis@wdc.com>; Bin Meng <bin.meng@windriver.com>; > Yoshinori Sato <ysato@users.sourceforge.jp>; Mark Cave-Ayland > <mark.cave-ayland@ilande.co.uk>; Artyom Tarasenko > <atar4qemu@gmail.com>; Bastian Koppelmann <kbastian@mail.uni- > paderborn.de>; Max Filippov <jcmvbkbc@gmail.com>; qemu- > arm@nongnu.org; qemu-ppc@nongnu.org; qemu-riscv@nongnu.org > Subject: [PATCH for-8.0 05/19] target/hexagon: Convert to 3-phase reset > > Convert the hexagon CPU class to use 3-phase reset, so it doesn't need to > use device_class_set_parent_reset() any more. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/hexagon/cpu.h | 2 +- > target/hexagon/cpu.c | 12 ++++++++---- > 2 files changed, 9 insertions(+), 5 deletions(-) > Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2a65a57bab3..794a0453fd4 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -137,7 +137,7 @@ typedef struct HexagonCPUClass { CPUClass parent_class; /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; } HexagonCPUClass; struct ArchCPU { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 03221fbdc28..658ca4ff783 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -281,14 +281,16 @@ static void hexagon_restore_state_to_opc(CPUState *cs, env->gpr[HEX_REG_PC] = data[0]; } -static void hexagon_cpu_reset(DeviceState *dev) +static void hexagon_cpu_reset_hold(Object *obj) { - CPUState *cs = CPU(dev); + CPUState *cs = CPU(obj); HexagonCPU *cpu = HEXAGON_CPU(cs); HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(cpu); CPUHexagonState *env = &cpu->env; - mcc->parent_reset(dev); + if (mcc->parent_phases.hold) { + mcc->parent_phases.hold(obj); + } set_default_nan_mode(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); @@ -339,11 +341,13 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c); + ResettableClass *rc = RESETTABLE_CLASS(c); device_class_set_parent_realize(dc, hexagon_cpu_realize, &mcc->parent_realize); - device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, + &mcc->parent_phases); cc->class_by_name = hexagon_cpu_class_by_name; cc->has_work = hexagon_cpu_has_work;
Convert the hexagon CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/hexagon/cpu.h | 2 +- target/hexagon/cpu.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-)