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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f14-20020a05600c154e00b003c6f3e5ba42sm6212559wmg.46.2022.11.24.03.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Nov 2022 03:50:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Taylor Simpson , Song Gao , Xiaojuan Yang , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Bin Meng , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH for-8.0 13/19] target/ppc: Convert to 3-phase reset Date: Thu, 24 Nov 2022 11:50:16 +0000 Message-Id: <20221124115023.2437291-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221124115023.2437291-1-peter.maydell@linaro.org> References: <20221124115023.2437291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the ppc CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz --- target/ppc/cpu-qom.h | 4 ++-- target/ppc/cpu_init.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 89ff88f28c9..0fbd8b72468 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -143,7 +143,7 @@ typedef struct PPCHash64Options PPCHash64Options; /** * PowerPCCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * A PowerPC CPU model. */ @@ -154,7 +154,7 @@ struct PowerPCCPUClass { DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; - DeviceReset parent_reset; + ResettablePhases parent_phases; void (*parent_parse_features)(const char *type, char *str, Error **errp); uint32_t pvr; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index cbf00813743..95d25856a0e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7031,16 +7031,18 @@ static bool ppc_cpu_has_work(CPUState *cs) return cs->interrupt_request & CPU_INTERRUPT_HARD; } -static void ppc_cpu_reset(DeviceState *dev) +static void ppc_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(dev); + CPUState *s = CPU(obj); PowerPCCPU *cpu = POWERPC_CPU(s); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; target_ulong msr; int i; - pcc->parent_reset(dev); + if (pcc->parent_phases.hold) { + pcc->parent_phases.hold(obj); + } msr = (target_ulong)0; msr |= (target_ulong)MSR_HVB; @@ -7267,6 +7269,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, ppc_cpu_realize, &pcc->parent_realize); @@ -7275,7 +7278,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) pcc->pvr_match = ppc_pvr_match_default; device_class_set_props(dc, ppc_cpu_properties); - device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, + &pcc->parent_phases); cc->class_by_name = ppc_cpu_class_by_name; cc->has_work = ppc_cpu_has_work;