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[PULL,09/30] target/arm: Add isar predicates for FEAT_HAFDBS

Message ID 20221025163952.4131046-10-peter.maydell@linaro.org
State Accepted
Commit 980a68925c8f19ae181c226af0776c0e3ddd0264
Headers show
Series [PULL,01/30] target/arm: Implement FEAT_E0PD | expand

Commit Message

Peter Maydell Oct. 25, 2022, 4:39 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>

The MMFR1 field may indicate support for hardware update of
access flag alone, or access flag and dirty bit.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 10 ++++++++++
 1 file changed, 10 insertions(+)
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Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f8c59858063..592b4ffbad4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4144,6 +4144,16 @@  static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
 }
 
+static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
+}
+
+static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
+}
+
 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;