From patchwork Fri Oct 21 07:15:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 617129 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp803486pvb; Fri, 21 Oct 2022 00:54:59 -0700 (PDT) X-Google-Smtp-Source: AMsMyM77EfGXKiNfuF0oTWZ+TZRMrU2ASh+fTwhoGrGMRpPTgSHjIOmxkHUmtrpAjjOnrKG154uq X-Received: by 2002:a05:622a:51:b0:39a:3854:5a34 with SMTP id y17-20020a05622a005100b0039a38545a34mr15301417qtw.143.1666338899031; Fri, 21 Oct 2022 00:54:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666338899; cv=none; d=google.com; s=arc-20160816; b=uUXhmpv9GwE7RlFd2ycU+hVDGjGFK5h1znunWJpfA1n+NS/nTEWxX6tijiTaXJ2EWe F9umXkfbMJSRTbufQ+vGv5sPZp4PAOBue8znBo+bQ0j1i1BkpEXKUAe9V+ygyloOVb6G 6txHuTIWoEons9jE5ESJleZhzfXlabpzEgBL/O7DnMRspRpXE+1spn3SUtzuc0Cf3LsO tnjXHe797T2V3fxIPvUpvp10qTS+zbDtx3sCjs1NRPcH9eICa3JGpzm1egd3I1rEU7nf Fdqqudo1y9DWAQc/SPzr/SCrhy6prg9LnqdmWBZeO6inLjiEc7WidUS3C6ESr22C0o3p izyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6MECj/5wfaqJXkyCl06/YPafA19dUtMTe/s1ymy0xIM=; b=cSTwpkG9tNfnl6Ko7RDYGMHmJ4s5PF76h/El+ACnlz41cA2xxGe0jcB71CXnzcB/Fe JU7NsCo0Ra4UaZTAhg6KmZNGWZsmQkVyURPyhJDx/LLLKSXXYAAVT2bvc5jwF5DriXbA cU3acyotCGYFLGartj1Dh1UBhPaNGE3O6t5kBpCsmaSGBfo9X3ttgECtX188aj1MQO6k zBpzlZfX3abGl62nFbNFjWRYNDU4s07SnkBiBYVBUJ58XejyjB3XN+dRLHVM4xsDLS4B V7YP1mIBHh4AFcj0ATQe98y/sTn1l6LYM5ngKYrcOnxacL2jRua0wx3kDbr6Udg0ZGFH VtzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CrlTmmx3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 11-20020a05621420cb00b004acc649925fsi2615506qve.479.2022.10.21.00.54.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Oct 2022 00:54:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CrlTmmx3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olmrj-0006Wh-Jm for patch@linaro.org; Fri, 21 Oct 2022 03:54:51 -0400 Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olmI9-0003Sz-Je for patch@linaro.org; Fri, 21 Oct 2022 03:18:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olmI4-0003Ry-EZ for qemu-devel@nongnu.org; Fri, 21 Oct 2022 03:18:00 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1olmI2-0005vR-F8 for qemu-devel@nongnu.org; Fri, 21 Oct 2022 03:18:00 -0400 Received: by mail-pl1-x633.google.com with SMTP id u6so1552755plq.12 for ; Fri, 21 Oct 2022 00:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6MECj/5wfaqJXkyCl06/YPafA19dUtMTe/s1ymy0xIM=; b=CrlTmmx3I7+eSr7GU/ObuF0y85aF3WFpnwnCr5iRag0VCAM4mZrQuahh5c1wxRfoqJ B/AEJ6VogTdb9N4YndC6jScUK2agdqUcC5cPu0c9G8QMyT2PCm3WMi5+5YBrp/yVT+/m MG/EOhoYHC8sV6dHErvRzlL9iju3l1USrsZ+7sUCdExKlrQva1hejV5tD14QIvBz15Sn 5DXgV9SFx8nkBRsc6zYD5vj4WBVOUOtj8QZswVkfew2Af7DF974aP4gSgh1an4KultjK sEw9PBqiSNST5T08BM7kUk5uIvoryi4hZ36lyVF3xzKFM95JVEvIPx6hOj+opYWfrYdQ jcgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6MECj/5wfaqJXkyCl06/YPafA19dUtMTe/s1ymy0xIM=; b=xwKHXZwMXszwi5aISLRpqlU57tlbwoBRAG+3HbmP0hxDo4EnGEycSbgTpvbd7Tl9CP Ih/iPJ04mD4fXnC0shtakhi6vYumw0YNgTOS1P4E2E8DCFM6F3din1ZQHGORQAmZsPEf mbz8iNiZCItvTl5i/4A1NonaXMfXvM0Jm9CuzcVGfNTbSyPRThpZL2ABVX+xdlw75BkE dv2dBHcSWxzmYLY2q41GQHP3uVGqZshzkENtQJnX4YsHl/8WDSj3Hr9lDVvJFNLqd3vd PJQ/xFJcGN5sGqT5s76r5Dgu+j/WESYO74S8Q0SXLHiMagv9UKmf5R5bpWsso7ZBcNJ/ F6lg== X-Gm-Message-State: ACrzQf2J+VyJcPScsOoiiKeLN2b5ySmC/VpUgvJUgXWEFWwthMF+zsNI ZAD2jKNWcn5TXIHkwaNhrQzsNyePgDnLNdMu X-Received: by 2002:a17:90b:4b10:b0:20c:c3a8:38e with SMTP id lx16-20020a17090b4b1000b0020cc3a8038emr20112935pjb.195.1666336676966; Fri, 21 Oct 2022 00:17:56 -0700 (PDT) Received: from localhost.localdomain ([149.135.10.35]) by smtp.gmail.com with ESMTPSA id q9-20020a638c49000000b0041cd5ddde6fsm13003327pgn.76.2022.10.21.00.17.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 00:17:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 34/36] tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Fri, 21 Oct 2022 17:15:47 +1000 Message-Id: <20221021071549.2398137-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021071549.2398137-1-richard.henderson@linaro.org> References: <20221021071549.2398137-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fill in the parameters for the host ABI for Int128 for those backends which require no extra modification. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 3 +++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tcg.c | 11 ++++++----- tcg/ppc/tcg-target.c.inc | 3 +++ 9 files changed, 24 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 413a5410c5..0dff5807f6 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -54,6 +54,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b7843d2d54..6613d3d791 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -91,6 +91,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF /* optional instructions */ #define TCG_TARGET_HAS_ext8s_i32 1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 74fbb22dfd..54e3478355 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -91,6 +91,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 15721c3e42..b235cba8ba 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -89,6 +89,8 @@ typedef enum { # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 232537ccea..d61ca902d3 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -85,9 +85,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS == 32 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index db5665c375..9a3856f0b3 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -168,6 +168,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_CALL_STACK_OFFSET 160 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_RET_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 0044ac8d78..53cfa843da 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -73,6 +73,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #if defined(__VIS__) && __VIS__ >= 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index f921a5ca24..7cde82f12d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -760,12 +760,13 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: /* - * No matter the call return method, we must have all of - * the temp subindexes in the call for liveness. + * For 32-bit hosts, do not split out individual temps. + * For 64-bit hosts, we need to add both temps for liveness + * no matter the backend calling convention. */ info->nr_out = TCG_TARGET_REG_BITS == 32 ? 1 : 2; - info->out_kind = TCG_CALL_RET_NORMAL; /* TODO */ - switch (/* TODO */ TCG_CALL_RET_NORMAL) { + info->out_kind = TCG_TARGET_CALL_RET_I128; + switch (TCG_TARGET_CALL_RET_I128) { case TCG_CALL_RET_NORMAL: if (TCG_TARGET_REG_BITS == 32) { info->out_kind = TCG_CALL_RET_NORMAL_4; @@ -827,7 +828,7 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: type = TCG_TYPE_I128; - kind = TCG_CALL_ARG_NORMAL; /* TODO */ + kind = TCG_TARGET_CALL_ARG_I128; break; default: g_assert_not_reached(); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 781ecfe161..e86d4a5e78 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -54,6 +54,9 @@ #else # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +/* Note sysv arg alignment applies only to 2-word types, not more. */ +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* For some memory operations, we need a scratch that isn't R0. For the AIX calling convention, we can re-use the TOC register since we'll be reloading