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[209.51.188.17]) by mx.google.com with ESMTPS id lk5-20020a0562145cc500b004ba89576be8si300304qvb.322.2022.10.20.15.44.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 20 Oct 2022 15:44:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lA9UPzaD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oleGq-0007j9-Cg for patch@linaro.org; Thu, 20 Oct 2022 18:44:12 -0400 Received: from [::1] (helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oleA8-00087D-4Q for patch@linaro.org; Thu, 20 Oct 2022 18:37:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oleA3-0007xa-Il for qemu-devel@nongnu.org; Thu, 20 Oct 2022 18:37:11 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oleA1-0000ya-Tl for qemu-devel@nongnu.org; Thu, 20 Oct 2022 18:37:11 -0400 Received: by mail-pj1-x102f.google.com with SMTP id z5-20020a17090a8b8500b00210a3a2364fso3244091pjn.0 for ; Thu, 20 Oct 2022 15:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=baaju4aj7L4HzLV2vbLThQkoFij3/vaMLp/lMiDo+UM=; b=lA9UPzaDusMswbXBHfTAZfhirWX/cdO35kvUE8CeI7KJ9UvxjLcR61C2v9zF1NB6WD 4zJv0GpgGA2JoiCrowGx/dLUCFvmqyVnHN9cjYe4g2rCNd3T/j/tbIuxzAVJYs7s7MjY h+3lqjR37YtHmFNth/4KzR3GC9lz5jhAHRuAvr8hS7XESfZZ5hIi8bDsp/Vs6AeaR6lL WNoRI4Oi2bv4pWG39T3qC0iv+69hFiUP9KnjnnIiyIbpyd2DOJNy/XXPBxmBO9tkwd5Z 0iXRVPtE6ZM3fUwi0nKJhSfms1oxD9DO+sFIaVJ9vEAuqLz+dK0lFkwPuPN2tO5QnTRO oHSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=baaju4aj7L4HzLV2vbLThQkoFij3/vaMLp/lMiDo+UM=; b=ZnYUl9t3gfLi8l/fgR0UlFqNEd0pqIDgqPArMghNLZvkFE4X3gQNWFjY5snDx4luK7 IRoypeUcl+tE0zEl4/u4OpL4hUVM76YZVMIaLkSpCxX+bbJNW4PKHJaQ+dVfYBpSSRqm wk6gBau7vV1RT/r/TK4cVkhWMzunsSxV6kbIx1soDXwPag/ErD8+wKT9e4edsGSWFTxs aKht97k0gU4enU87S5aCFNQDbinlD6C2MDhbQeYoOSN1yPwaTaMLyOU1CBtptnvtQW0y Q4CLXJJn8qlNBE3MCCI/ffX/lexrSSRV6ND4bKQR2L0yfRb2N2KPFQaIGTw53hQNZK/e qSgg== X-Gm-Message-State: ACrzQf2pTwB/rjOohpVn0NMViAtg7V4IyOSSpeD5htNm8iDZ5DaP8JoX JkGjWgBwgkwDY0Z0n7ocwNF3PeX4fhGa4lPL X-Received: by 2002:a17:90a:4ec6:b0:20a:96cd:2a46 with SMTP id v6-20020a17090a4ec600b0020a96cd2a46mr18876074pjl.171.1666305429062; Thu, 20 Oct 2022 15:37:09 -0700 (PDT) Received: from localhost.localdomain ([149.135.10.35]) by smtp.gmail.com with ESMTPSA id r10-20020aa7988a000000b0054cd16c9f6bsm13753841pfl.200.2022.10.20.15.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 15:37:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v5 13/14] target/arm: Implement FEAT_HAFDBS, dirty bit portion Date: Fri, 21 Oct 2022 08:35:47 +1000 Message-Id: <20221020223548.2310496-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020223548.2310496-1-richard.henderson@linaro.org> References: <20221020223548.2310496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Perform the atomic update for hardware management of the dirty bit. Signed-off-by: Richard Henderson --- v5: Move the DB update before attributes are extracted and merged. --- target/arm/cpu64.c | 2 +- target/arm/ptw.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fe1369fe96..0732796559 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1165,7 +1165,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; - t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 1); /* FEAT_HAFDBS, AF only */ + t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 209ea7024b..1c1f0bfa1a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1463,6 +1463,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, goto do_fault; } } + + /* + * Dirty Bit. + * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP + * bit for writeback. The actual write protection test may still be + * overridden by tableattrs, to be merged below. + */ + if (param.hd + && extract64(descriptor, 51, 1) /* DBM */ + && access_type == MMU_DATA_STORE) { + if (regime_is_stage2(mmu_idx)) { + new_descriptor |= 1ull << 7; /* set S2AP[1] */ + } else { + new_descriptor &= ~(1ull << 7); /* clear AP[2] */ + } + } } /*