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Thu, 20 Oct 2022 04:59:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5FFB91FFCF; Thu, 20 Oct 2022 12:52:12 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: fam@euphon.net, berrange@redhat.com, f4bug@amsat.org, aurelien@aurel32.net, pbonzini@redhat.com, stefanha@redhat.com, crosa@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , David Hildenbrand , Cornelia Huck , Thomas Huth , qemu-s390x@nongnu.org (open list:S390 TCG CPUs) Subject: [PATCH v3 25/26] target/s390x: fake instruction loading when handling 'ex' Date: Thu, 20 Oct 2022 12:52:08 +0100 Message-Id: <20221020115209.1761864-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020115209.1761864-1-alex.bennee@linaro.org> References: <20221020115209.1761864-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The s390x EXecute instruction is a bit weird as we synthesis the executed instruction from what we have stored in memory. This missed the plugin instrumentation. Work around this with a special helper to inform the rest of the translator about the instruction so things stay consistent. Signed-off-by: Alex Bennée Cc: Richard Henderson Reviewed-by: Richard Henderson Acked-by: Ilya Leoshkevich --- v2 - s/w/b/ for translator_fake_ldb - add comment to extract_insn - reword commit message --- include/exec/translator.h | 17 +++++++++++++++++ target/s390x/tcg/translate.c | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/include/exec/translator.h b/include/exec/translator.h index 3b77f5f4aa..af2ff95cd5 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -211,6 +211,23 @@ translator_ldq_swap(CPUArchState *env, DisasContextBase *db, return ret; } +/** + * translator_fake_ldb - fake instruction load + * @insn8: byte of instruction + * @pc: program counter of instruction + * + * This is a special case helper used where the instruction we are + * about to translate comes from somewhere else (e.g. being + * re-synthesised for s390x "ex"). It ensures we update other areas of + * the translator with details of the executed instruction. + */ + +static inline void translator_fake_ldb(uint8_t insn8, abi_ptr pc) +{ + plugin_insn_append(pc, &insn8, sizeof(insn8)); +} + + /* * Return whether addr is on the same page as where disassembly started. * Translators can use this to enforce the rule that only single-insn diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 95279e5dc3..8101f5f569 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6317,12 +6317,18 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s) if (unlikely(s->ex_value)) { /* Drop the EX data now, so that it's clear on exception paths. */ TCGv_i64 zero = tcg_const_i64(0); + int i; tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value)); tcg_temp_free_i64(zero); /* Extract the values saved by EXECUTE. */ insn = s->ex_value & 0xffffffffffff0000ull; ilen = s->ex_value & 0xf; + /* register insn bytes with translator so plugins work */ + for (i = 0; i < ilen; i++) { + uint8_t byte = extract64(insn, 56 - (i * 8), 8); + translator_fake_ldb(byte, pc + i); + } op = insn >> 56; } else { insn = ld_code2(env, s, pc);