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([2605:ef80:8002:3cad:72cd:dd96:98f6:c3cf]) by smtp.gmail.com with ESMTPSA id 135-20020a62168d000000b0056025ccc3bbsm2749783pfw.146.2022.10.02.10.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Oct 2022 10:30:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 9/9] target/i386: Use probe_access_full for final stage2 translation Date: Sun, 2 Oct 2022 10:29:56 -0700 Message-Id: <20221002172956.265735-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221002172956.265735-1-richard.henderson@linaro.org> References: <20221002172956.265735-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than recurse directly on mmu_translate, go through the same softmmu lookup that we did for the page table walk. This centralizes all knowledge of MMU_NESTED_IDX, with respect to setup of TranslationParams, to get_physical_address. Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 40 +++++++++++++++++++--------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index e8457e9b21..d51b5d7431 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -143,7 +143,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in, .err = err, .ptw_idx = in->ptw_idx, }; - hwaddr pte_addr; + hwaddr pte_addr, paddr; uint32_t pkr; int page_size; @@ -420,33 +420,47 @@ do_check_protect_pse36: } /* align to page_size */ - out->paddr = (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) - | (addr & (page_size - 1)); + paddr = (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1)) + | (addr & (page_size - 1)); if (in->ptw_idx == MMU_NESTED_IDX) { - TranslateParams nested_in = { - .addr = out->paddr, - .access_type = access_type, - .cr3 = env->nested_cr3, - .pg_mode = env->nested_pg_mode, - .mmu_idx = MMU_USER_IDX, - .ptw_idx = MMU_PHYS_IDX, - }; + CPUTLBEntryFull *full; + int flags, nested_page_size; - if (!mmu_translate(env, &nested_in, out, err)) { + flags = probe_access_full(env, paddr, access_type, + MMU_NESTED_IDX, true, + &pte_trans.haddr, &full, 0); + if (unlikely(flags & TLB_INVALID_MASK)) { + err->exception_index = 0; /* unused */ + err->error_code = env->error_code; + err->cr2 = paddr; err->stage2 = S2_GPA; return false; } /* Merge stage1 & stage2 protection bits. */ - prot &= out->prot; + prot &= full->prot; /* Re-verify resulting protection. */ if ((prot & (1 << access_type)) == 0) { goto do_fault_protect; } + + /* Merge stage1 & stage2 addresses to final physical address. */ + nested_page_size = 1 << full->lg_page_size; + paddr = (full->phys_addr & ~(nested_page_size - 1)) + | (paddr & (nested_page_size - 1)); + + /* + * Use the larger of stage1 & stage2 page sizes, so that + * invalidation works. + */ + if (nested_page_size > page_size) { + page_size = nested_page_size; + } } + out->paddr = paddr; out->prot = prot; out->page_size = page_size; return true;