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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 34/42] target/arm: Move be test for regime into S1TranslateResult Date: Sat, 1 Oct 2022 09:23:10 -0700 Message-Id: <20221001162318.153420-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 99ad894180..d356b0b22d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -222,6 +222,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) typedef struct { bool is_secure; + bool be; void *hphys; hwaddr gphys; } S1TranslateResult; @@ -301,6 +302,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, !(pte_secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW)); + res->be = regime_translation_big_endian(env, mmu_idx); return true; fail: @@ -320,7 +322,6 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, CPUState *cs = env_cpu(env); S1TranslateResult s1; uint32_t data; - bool be; if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, debug, &s1, fi)) { @@ -329,10 +330,9 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, return 0; } - be = regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data = ldl_be_p(s1.hphys); } else { data = ldl_le_p(s1.hphys); @@ -343,7 +343,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; - if (be) { + if (s1.be) { data = address_space_ldl_be(as, s1.gphys, attrs, &result); } else { data = address_space_ldl_le(as, s1.gphys, attrs, &result); @@ -364,7 +364,6 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, CPUState *cs = env_cpu(env); S1TranslateResult s1; uint64_t data; - bool be; if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, debug, &s1, fi)) { @@ -373,10 +372,9 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, return 0; } - be = regime_translation_big_endian(env, mmu_idx); if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ - if (be) { + if (s1.be) { data = ldq_be_p(s1.hphys); } else { data = ldq_le_p(s1.hphys); @@ -387,7 +385,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; - if (be) { + if (s1.be) { data = address_space_ldq_be(as, s1.gphys, attrs, &result); } else { data = address_space_ldq_le(as, s1.gphys, attrs, &result);