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([2605:ef80:8084:91a4:f7cb:db31:c505:b931]) by smtp.gmail.com with ESMTPSA id t4-20020a37ea04000000b006d1d8fdea8asm4387445qkj.85.2022.10.01.09.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 09:24:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 33/42] target/arm: Split out S1TranslateResult type Date: Sat, 1 Oct 2022 09:23:09 -0700 Message-Id: <20221001162318.153420-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221001162318.153420-1-richard.henderson@linaro.org> References: <20221001162318.153420-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Consolidate the results of S1_ptw_translate in one struct. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 70 +++++++++++++++++++++++++----------------------- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7a77bea2c7..99ad894180 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -220,13 +220,18 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) } } +typedef struct { + bool is_secure; + void *hphys; + hwaddr gphys; +} S1TranslateResult; + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, ARMMMUIdx s2_mmu_idx, hwaddr addr, - bool *is_secure_ptr, void **hphys, hwaddr *gphys, - bool debug, ARMMMUFaultInfo *fi) + bool is_secure, bool debug, + S1TranslateResult *res, ARMMMUFaultInfo *fi) { - bool is_secure = *is_secure_ptr; uint8_t pte_attrs; bool s2_phys, pte_secure; @@ -238,7 +243,7 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, * state of the cpu at all, including softmmu tlb contents. */ if (s2_phys) { - *gphys = addr; + res->gphys = addr; pte_attrs = 0; pte_secure = is_secure; } else { @@ -251,11 +256,11 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, &s2, fi)) { goto fail; } - *gphys = s2.f.phys_addr; + res->gphys = s2.f.phys_addr; pte_attrs = s2.cacheattrs.attrs; pte_secure = s2.f.attrs.secure; } - *hphys = NULL; + res->hphys = NULL; } else { CPUTLBEntryFull *full; int flags; @@ -263,13 +268,13 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, env->tlb_fi = fi; flags = probe_access_full(env, addr, MMU_DATA_LOAD, arm_to_core_mmu_idx(s2_mmu_idx), - true, hphys, &full, 0); + true, &res->hphys, &full, 0); env->tlb_fi = NULL; if (unlikely(flags & TLB_INVALID_MASK)) { goto fail; } - *gphys = full->phys_addr; + res->gphys = full->phys_addr; pte_attrs = full->pte_attrs; pte_secure = full->attrs.secure; } @@ -291,12 +296,11 @@ static bool S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, } } - if (is_secure) { - /* Check if page table walk is to secure or non-secure PA space. */ - *is_secure_ptr = !(pte_secure - ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW); - } + /* Check if page table walk is to secure or non-secure PA space. */ + res->is_secure = (is_secure && + !(pte_secure + ? env->cp15.vstcr_el2 & VSTCR_SW + : env->cp15.vtcr_el2 & VTCR_NSW)); return true; fail: @@ -314,36 +318,35 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, bool debug, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint32_t data; bool be; - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, debug, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, + debug, &s1, fi)) { /* Failure. */ assert(fi->s1ptw); return 0; } be = regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data = ldl_be_p(hphys); + data = ldl_be_p(s1.hphys); } else { - data = ldl_le_p(hphys); + data = ldl_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = is_secure }; + MemTxAttrs attrs = { .secure = s1.is_secure }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; if (be) { - data = address_space_ldl_be(as, gphys, attrs, &result); + data = address_space_ldl_be(as, s1.gphys, attrs, &result); } else { - data = address_space_ldl_le(as, gphys, attrs, &result); + data = address_space_ldl_le(as, s1.gphys, attrs, &result); } if (unlikely(result != MEMTX_OK)) { fi->type = ARMFault_SyncExternalOnWalk; @@ -359,36 +362,35 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, bool debug, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - void *hphys; - hwaddr gphys; + S1TranslateResult s1; uint64_t data; bool be; - if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, &is_secure, - &hphys, &gphys, debug, fi)) { + if (!S1_ptw_translate(env, mmu_idx, ptw_idx, addr, is_secure, + debug, &s1, fi)) { /* Failure. */ assert(fi->s1ptw); return 0; } be = regime_translation_big_endian(env, mmu_idx); - if (likely(hphys)) { + if (likely(s1.hphys)) { /* Page tables are in RAM, and we have the host address. */ if (be) { - data = ldq_be_p(hphys); + data = ldq_be_p(s1.hphys); } else { - data = ldq_le_p(hphys); + data = ldq_le_p(s1.hphys); } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = is_secure }; + MemTxAttrs attrs = { .secure = s1.is_secure }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; if (be) { - data = address_space_ldq_be(as, gphys, attrs, &result); + data = address_space_ldq_be(as, s1.gphys, attrs, &result); } else { - data = address_space_ldq_le(as, gphys, attrs, &result); + data = address_space_ldq_le(as, s1.gphys, attrs, &result); } if (unlikely(result != MEMTX_OK)) { fi->type = ARMFault_SyncExternalOnWalk;