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[PULL,10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP

Message ID 20220930133511.2112734-11-peter.maydell@linaro.org
State Accepted
Commit beeec926d24aac28f95cc7694ef3837d7a4cd3bb
Headers show
Series [PULL,01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO | expand

Commit Message

Peter Maydell Sept. 30, 2022, 1:35 p.m. UTC 
From: Jerome Forissier <jerome.forissier@linaro.org>

SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
it with ARM_CP_EL3_NO_EL2_KEEP.

Cc: qemu-stable@nongnu.org
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 24c592ffef8..db3b1ea72da 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5088,7 +5088,7 @@  static const ARMCPRegInfo v8_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .type = ARM_CP_ALIAS,
+      .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,