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[209.51.188.17]) by mx.google.com with ESMTPS id c5-20020a05620a268500b006ce5ba64da7si9172301qkp.555.2022.09.26.06.50.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Sep 2022 06:50:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y9kyFXT2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ocoUr-0006tL-Vl for patch@linaro.org; Mon, 26 Sep 2022 09:50:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ocoKK-00023d-OS for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:17 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:44581) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ocoKH-0005f6-5u for qemu-devel@nongnu.org; Mon, 26 Sep 2022 09:39:16 -0400 Received: by mail-wm1-x32e.google.com with SMTP id k3-20020a05600c1c8300b003b4fa1a85f8so3735682wms.3 for ; Mon, 26 Sep 2022 06:39:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=aG890OAM4la1STKlhUzUAHk//B/vPqbxIBEMPlxySJs=; b=Y9kyFXT2Uq22TnF+aX55a7s+xxPR+k8s0XRTkOgZVwXXHE4Jsqmf3VbGd/M6Cwpmdo imDE17hiMZhPscidbf8SbXi+yXzkklCT8eEGD4Y6nMEuNQZp89ZEdaRglpzj/m8Llv2Z VYHWuovZlFIog9fPK8RElB42zIYHvsywEUJluGItpm8qVcawDGSAoK1tG9jfRBT4m+Hl UvcgQMCIN3UzUBJB79yl7kLPIeqvUl3fXRQJWcMnIikckKHj0gZ44saiZMw1h5uURbVi mIb6Gqfgx+Ynyw34kyUPi7oKddZUilcfGAcxlJa4nUJHUau8UWrxhyR0gGGbIty55Beh UjSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=aG890OAM4la1STKlhUzUAHk//B/vPqbxIBEMPlxySJs=; b=5XYJ/680WBd/o+x6j/pQz8B/0i7MtJb8TdfPfAIASgwEh1Unpo4jbip6eO/pfiNYXR wPU3Otydsz0350t7Zc4dlnEKHBSkDEmYJg9ZyVDkDQBI4ro+wr2vk3DQ+h4tHWdlW4aY Xnf2bIEW7ex4/r/lSG8Y2l5gHk/KHco8xqx0xODAkhoIr0yPai4IWHsvHhcS8oGRCfMq yoM7tB7E8Rvryg+Szf+eFxC4ysQga0RKxraixUc+DSt39fwwELmhgy/DQGzrmqt5/oz1 /ie0TfPqsyjy0ELEdF7jOO3mg9EpCEwLufBPxFrhOu66/mIa75AhCdF6D2lIhs5sMXK6 6NcA== X-Gm-Message-State: ACrzQf19JhZvMDcMFydlsekUK1vGQmoQ8BYda5OU7NTVhzii+KN0VrLp U+pQIsBgKQL3oLNFPke+t6AitQ== X-Received: by 2002:a05:600c:a49:b0:3a6:673a:2a9b with SMTP id c9-20020a05600c0a4900b003a6673a2a9bmr21643143wmq.3.1664199550606; Mon, 26 Sep 2022 06:39:10 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id p8-20020a05600c1d8800b003a342933727sm11844696wms.3.2022.09.26.06.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Sep 2022 06:39:08 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2E1041FFBD; Mon, 26 Sep 2022 14:39:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson , Peter Maydell Subject: [PATCH v2 05/11] hw/intc/gic: use MxTxAttrs to divine accessing CPU Date: Mon, 26 Sep 2022 14:38:58 +0100 Message-Id: <20220926133904.3297263-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org> References: <20220926133904.3297263-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 --- v2 - update for new field - bool asserts --- hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab..d907df3884 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -static inline int gic_get_current_cpu(GICState *s) +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; - } - return 0; + /* + * Something other than a CPU accessing the GIC would be a bug as + * would a CPU index higher than the GICState expects to be + * handling + */ + g_assert(attrs.requester_type == MEMTXATTRS_CPU); + g_assert(attrs.requester_id < s->num_cpu); + + return attrs.requester_id; } -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } /* Return true if this GIC config has interrupt groups, which is @@ -951,7 +956,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) int cm; int mask; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); cm = 1 << cpu; if (offset < 0x100) { if (offset == 0) { /* GICD_CTLR */ @@ -1182,7 +1187,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, int i; int cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); if (offset < 0x100) { if (offset == 0) { if (s->security_extn && !attrs.secure) { @@ -1476,7 +1481,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, int mask; int target_cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); irq = value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1780,7 +1785,7 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1788,7 +1793,7 @@ static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1818,7 +1823,7 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1827,7 +1832,7 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, attrs); } static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1860,7 +1865,7 @@ static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) { - int vcpu = gic_get_current_vcpu(s); + int vcpu = gic_get_current_vcpu(s, attrs); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1995,7 +2000,7 @@ static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *dat { GICState *s = (GICState *)opaque; - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, @@ -2004,7 +2009,7 @@ static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data,